Electronic digital logic circuitry – Interface – Current driving
Patent
1997-10-27
2000-06-13
Medley, Sally C.
Electronic digital logic circuitry
Interface
Current driving
326 27, 326 83, 326 80, 326 81, H03K 190185
Patent
active
060753838
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Input/output circuits of semiconductor modules or chips are the link between the on-chip and off-chip signal levels or signals. The number of input/output circuits in this case depends on the function of the chip. These days, it is no longer unusual for there to be input/output ports of the order of magnitude of 100 terminals per chip, for example in digital exchanges. Wide bus lines on the printed circuit boards interconnect the individual components of a system. The trend here is toward transmission rates of ever higher frequency via the transmission lines of the bus. On account of interference immunity, the radio-frequency signals are additionally transmitted in a complementary manner, which again doubles the number of input/output ports.
Conventional CMOS output amplifiers (CMOS buffers) are not suitable for radio-frequency applications (>100 to 500 MHz) on account of the poor signal quality (overshoots/undershoots) and the high voltage swing. Radio-frequency signals are usually transmitted using ECL technology with terminated 50 .OMEGA. transmission lines. Terminated 50 .OMEGA. lines prevent reflection and thus distortion of the signals during transmission via the line. A disadvantage of ECL technology is the relatively high power loss, which, depending on the number of input/output ports, can become the determining factor of the total power loss of a module.
The open-collector technology which is employed in various standards (ECL standard=Emitter Coupled Logic; GTL standard=Gunning Transceiver Logic; CTT standard=Center Tap Terminated Digital Interface) is helpful for reducing the on-chip power loss. In this case, part of the power loss is transferred to an external resistor. However, the disadvantage of open-collector or open-drain technology is the limited suitability for radio frequencies, since the signal rise at the output is limited depending on the external resistor and load capacitance. Although the pull-down transistor of the output amplifier can be dimensioned such that the load capacitance of the line is discharged in an appropriate time, the rise time for the high level is determined by the RC time of the external resistor and load capacitance. If the external resistor is realized as a 50 .OMEGA. terminating resistor in order to avoid line reflections, as proposed for example by B. Gunning (B. Gunning, "CMOS Low-Voltage-Swing Transmission-Line Transceiver", ISSCC 92, pages 58 to 59), a load of 2.5 pF suffices to limit the switching frequency to approximately 500 MHz.
The problem on which the invention is based consists in specifying a GTL output amplifier for coupling an input signal present at the input into a transmission line present at the output, by means of which amplifier radio-frequency signals can also be switched on to the transmission line.
SUMMARY OF THE INVENTION
In general terms the present invention is a GTL output amplifier for coupling an input signal present at the input into a transmission line present at the output. A pull-down transistor applies a first potential to the output in the event of a first value of the input signal. A pull-up transistor circuit has a series circuit formed by a first transistor, which is switched off in the presence of the first value of the input signal and switched on in the presence of a second value of the input signal, and by a second transistor, whose input is connected to a delay circuit. The second transistor remains switched on for a time which is governed by the delay circuit, during a transition phase of the input signal from the first value, to the second value. The delay circuit is provided between input signal and the second transistor. The delay circuit switches off the second transistor when the second value of the input signal occurs and after the time governed by the delay circuit has elapsed. A third transistor is connected between the junction point of the two transistors of the series circuit and is switched on in the event of the first value of the input signal. The pull-up transistor
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Medley Sally C.
Siemens Aktiengesellschaft
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