Growth technique for preparing graded gap semiconductors and dev

Details Growth technique for preparing graded gap semiconductors and dev Growth technique for preparing graded gap semiconductors and dev

1977-12-27

1980-10-14

Kaplan, Morris

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

156611, 357 4, 357 16, 357 30, 357 61, H01L 21203

Patent

active

042279488

ABSTRACT:
A variable temperature method for the preparation of single and multiple taxial layers of single-phase (e.g., face-centered cubic), ternary lead chalcogenide alloys (e.g., lead cadmium sulfide, [Pb.sub.1-w Cd.sub.w ].sub.a [S].sub.1-a wherein w varies between zero and fifteen hundredths, inclusive, and a=0.500.+-.0.003), deposited upon substrates of barium fluoride, BaF.sub.2, maintained in near thermodynamic equilibrium with concurrently sublimated lead alloy and chalcogenide sources. During preparation, the temperature of the substrate is varied, thereby providing an epilayer with graded composition and predetermined electrical and optical properties along the direction of growth. This growth technique can be used to produce infrared lenses, narrowband detectors, and double heterojunction lasers.

REFERENCES:
patent: 3763070 (1974-02-01), Schoolar
patent: 3969743 (1976-07-01), Gorski
patent: 4053919 (1977-10-01), Andrews
patent: 4066481 (1978-01-01), Marascuit
patent: 4154631 (1979-05-01), Schoolar

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