Error detection method and apparatus for processor having main s

Details Error detection method and apparatus for processor having main s Error detection method and apparatus for processor having main s

1990-05-08

1992-12-15

Beausoliel, Robert W.

Excavating

371 161, 371 18, G06F 1100

Patent

active

051723786

ABSTRACT:
In an information processor having a central processing unit, a main storage which is accessed by the central processing unit, and an input/output processing unit which controls transfer of information between the central processing unit as well as the main storage and exterior of the information processor; a memory area of the main storage is partitioned into a software area and a hardware area, a train of instructions for inspecting the central processing unit, the main storage and the input/output processing unit are stored in the hardware area, and the central processing unit executes a program stored in the software area and the instruction train stored in the hardware area, alternately at desired intervals so as to decide existence or nonexistence of occurrence of an error on the basis of an executed result of the instruction train.

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