Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-17
2003-12-30
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S584000, C438S618000, C438S622000, C438S623000, C438S624000, C438S636000, C438S637000, C438S638000, C438S642000, C438S733000, C438S736000
Reexamination Certificate
active
06670271
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the fabrication of integrated circuit devices. In particular, the present invention relates to a method for fabricating interconnecting conductive lines and vias in a dual damascene structure.
BACKGROUND
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down (e.g., to submicron levels) device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required. These features sizes include the width and spacing of interconnecting lines, and the spacing and diameter of metal contact vias.
High resolution lithographic processes are employed to define patterns for interconnecting lines and vias. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist. The film is exposed with a radiation source (such as optical light, x-rays, or an electron beam) that irradiates selected areas of the surface through an intervening master template, the mask, forming a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through the mask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process leaving the less soluble photoresist forming a patterned coating.
A typical method of employing lithography to form metal lines and vias is to form the patterned resist coating over a dielectric layer, such as a layer of silicon oxide. An anisotropic etching process can then be employed to remove the dielectric where it is left exposed by the patterned resist coating. Thereby, the resist pattern is transfer to the dielectric layer. The photoresist is then stripped. A blanket coating of metal is applied over the dielectric layer, filling the gaps in the dielectric pattern. The metal layer is then polished or etched until only the portion of the metal within the pattern gaps remains. This is a single damascene process.
Where multilevel interconnections are desired, the single damascene process can be repeated. However, an improvement is a dual damascene process where two interconnect layers are formed at once. For example a layer of conductive vias and an overlying layer of conductive wiring can be formed simultaneously. A dual damascene process generally involves fewer steps than two single damascene processes. In addition, the dual damascene process eliminates the interface between the two layers.
In a conventional dual damascene process, an insulating layer is coated with a photoresist that is exposed through a first mask to pattern openings corresponding to vias. Anisotropic etching removes the dielectric beneath the patterned openings, thus transferring the via pattern into the dielectric layer. The photoresist is then exposed through a second mask with an image pattern corresponding to conductive lines aligned with the via openings. A second anisotropic etching process removes dielectric in a pattern corresponding to the conductive lines. This second etching process is controlled so that only a portion of the dielectric layer is removed where conductive lines are desired. Thus, trenches are formed in the dielectric which can be filled to form the conductive lines. Dielectric remains to insulate the conductive lines from the underlying substrate except where vias, corresponding to the first mask, are formed entirely through the dielectric layer.
A conventional dual damascene process is illustrated in
FIGS. 1-3
.
FIG. 1
is a perspective view illustration of a composite
10
including a dielectric layer
14
formed on a semiconductor substrate
12
. A photoresist layer
16
is formed on the dielectric layer
14
. The photoresist layer
16
is patterned to form first openings
18
. Anisotropic reactive ion etching (RIE) is performed to form vias
20
(
FIG. 2
) in the dielectric layer
14
. Subsequently, the photoresist
16
is exposed through a second mask to form opening
24
corresponding to conductive lines, as illustrated in FIG.
2
. RIE is again carried out, this time forming trenches
26
in the dielectric layer
14
as illustrated in FIG.
3
.
FIG. 3
illustrates the composite
10
after stripping the photoresist
16
.
While the conventional dual damascene process is workable, there remains room for improvement. The conventional dual damascene process involves dielectric etching and clean steps that are difficult to engineer; the process contributes significantly to the overall cost of integrated circuit devices; and the dimension of the resulting lines and vias limits the state of the art for integrated circuit devices. Thus, there remains an unmet need for improved processes for forming metal lines and vias.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some of its aspects. This summary is not an extensive overview of the invention and is intended neither to identify key or critical elements of the invention nor to delineate its scope. The primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention involves a method for fabricating interconnecting lines and vias. In a method of the invention, copper is grown from a seed layer to substantially fill openings in a two layer structure wherein the two layers are independently either dielectric or resist layers. According to one aspect of the invention, first and second resist layers are formed into a dual damascene structure. A copper seed layer is provided in the pattern gaps. Copper is grown by plating from the copper seed layer to form copper features that fill the pattern gaps. The resist is stripped, leaving the copper features. The copper features can then be coated with a diffusion barrier layer and a dielectric. Polished can be employed to planarize the dielectric layer and the copper features.
According to another aspect of the invention, a first resist is patterned over a substrate and a first dielectric coating is formed over the patterned first resist. Polishing leaves the first dielectric coating in the inverse pattern image. A second resist layer is formed and patterned over the first dielectric coating. The first patterned resist is stripped either before, during, or after patterning the second resist layer. A second dielectric layer is formed over the second patterned resist and polished to leave the second dielectric in the inverse pattern of the second patterned resist. The resists are stripped and copper features are grown from a copper seed layer within gaps of the first and second dielectric coatings.
According to a further aspect of the invention, a first resist is patterned over a substrate and a first dielectric coating is formed over the patterned resist. Polishing leaves the first dielectric coating in the inverse pattern image. A second resist layer is formed and patterned over the first dielectric coating. The first patterned resist is stripped either before, during, or after patterning the second resist layer. Copper features are grown from a copper seed layer within the gaps of the first dielectric layer and the second patterned resist. The second patterned resist is then stripped and a second dielectric layer is formed over the copper features and the first dielectric layer. Polishing can be employed to planarize the second dielectric layer and the copper featu
Rangarajan Bharath
Singh Bhanwar
Subramanian Ramkumar
Templeton Michael K.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Cuneo Kamand
Kilday Lisa
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