Group shifting and level shifting rotational arbiter system

Details Group shifting and level shifting rotational arbiter system Group shifting and level shifting rotational arbiter system

2000-09-29

2003-12-16

Rinehart, Mark H (Department: 2189)

Electrical computers and digital data processing systems: input/

Access arbitrating

C710S244000

Reexamination Certificate

active

06665760

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to arbiter systems for controlling access to hardware resources in a computer system. This invention also relates to error checking systems that generate error checking values to detect errors in the transmission of data.
2. Description of Related Art
Computer systems use communication systems to communicate information between different hardware resources. An example of a communication system is a direct memory access (DMA) communication system used to transfer information between hardware resources without involvement of a microprocessor, thereby freeing the microprocessor to perform other tasks. Typically, in DMA communication systems, there are numerous hardware resources that take turns accessing a common data bus. This process is performed under the control of an arbiter which decides which resource has access based on the priority levels of the various resources. In general, arbiters are used any time there are multiple resources that share access to a common resource.
Different arbiters employ different schemes to control access to a common resource such as a data bus. Fixed priority schemes are schemes in which the priority level assigned to individual resources is fixed. Thus, if a first resource has a higher priority than a second resource, then the second resource is not granted access to the data bus whenever the first resource is requesting access. Fixed priority schemes allow resources that communicate more time-sensitive data to be given higher priority access to the data bus, and resources that communicate less time-sensitive data to be given lower priority access to the data bus. Shifting priority schemes are schemes in which the highest priority level shifts between resources. For example, a round robin priority scheme may be employed to ensure that each resource is granted access to the data bus. Shifting priority schemes avoid starving a particular resource from lack of access to the data bus. The number and type of resources utilized, the type of priority scheme utilized, and the priorities assigned to individual resources are typically design choices based on the application for which the computer system is utilized.
Computer systems are now often implemented using “system-on-chip” integrated circuits. In a single chip, these integrated circuits provide many of the functions that used to be spread among many integrated circuits. For example, in addition to the main microprocessor, it is not uncommon to have other circuits such as specialized serial interfaces, UARTs, memory controllers, DMA controllers, Ethernet interfaces, display interfaces, USB (universal serial bus) interfaces, and so on.
It is generally desirable for system-on-chip integrated circuits to be usable in a wide array of applications. To this end, manufacturers of such integrated circuits commonly provide such integrated circuits with numerous hardware resources, recognizing that a given application may only utilize a particular combination of the resources, leaving the remaining resources unutilized. This presents a challenge from the standpoint of providing a DMA arbitration scheme, because the application for which the integrated circuit will be utilized, as well as the particular combination of hardware resources utilized, is unknown. A DMA system that is not properly matched to the hardware resources used in a particular application results in data being communicated in a non-optimal manner and degrades overall performance of the system-on-chip integrated circuit. Therefore, there is a need for a highly flexible arbiter system to provide for a more optimal utilization of hardware resources (e.g., DMA resources) in such circumstances.
It is also common to employ error checking schemes in communication systems to ensure that any errors that occur during the transfer of data are detected.
Examples of error checking schemes include CRC-16, CRC-16 Reverse, CRC-CCITT, CRC-CCITT Reverse, and CRC-32. Generally, error checking schemes operate by generating an error checking value as a function of the data that is transmitted. The bit length of the error checking value is typically short relative to the overall bit length of the transmitted data. Both parties to the transmission must generate the same value otherwise a transmission error has occurred. The error checking value can be generated using a microprocessor or using discrete logic circuitry such as a linear feedback shift register.
The type of error checking scheme that is employed in connection with a particular hardware resource is also application dependent. This, too, presents a challenge for the manufacturer of a system-on-chip integrated circuit. Given that a particular system-on-chip integrated circuit is liable to be employed in a wide array of applications, it is difficult to know in advance which hardware resources will be utilized, let alone which error checking schemes will be required for the hardware resources that are utilized. To address this problem, system-on-chip integrated circuits have typically relied on the microprocessor of the system-on-chip integrated circuit instead of discrete logic circuitry to generate error checking values. However, this approach places a significant burden the microprocessor and degrades the overall performance of the system-on-chip integrated circuit. Therefore, what is also needed is a flexible error checking value generator circuit, especially one that can be used with a general purpose DMA controller.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a system comprises a plurality of hardware resources, a common resource, and an arbiter. The plurality of hardware resources are divided into groups of hardware resources. The common resource is coupled to the plurality of hardware resources. The arbiter is coupled to the plurality of resources, and controls which of the plurality of hardware resources has priority to access to the common resource. The arbiter includes a group shifting arbiter and a level shifting arbiter. The group shifting arbiter shifts priority among the groups of hardware resources. The level shifting arbiter separately shifts priority among the hardware resources within each of the groups.
According to a second the invention, a system comprises a general purpose DMA controller and an arithmetic circuit. The arithmetic circuit is coupled to receive data from the general purpose DMA controller. The arithmetic circuit generates an error checking value based on the data received from the general purpose DMA controller and based on a polynomial equation. The arithmetic circuit is capable of being programmed with a plurality of different polynomial equations usable to generate error checking values of different types.


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