Group-III nitride semiconductor stack, method of...

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate

Reexamination Certificate

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C438S046000, C438S047000, C257SE21085, C257SE21097, C257SE21126, C257SE21155

Reexamination Certificate

active

07550368

ABSTRACT:
A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.

REFERENCES:
patent: 5874747 (1999-02-01), Redwing et al.
patent: 6072189 (2000-06-01), Duggan
patent: 2000049377 (2000-02-01), None
patent: 2000133842 (2000-05-01), None
Iwaya, et al., “Reduction of Etch Pit Density in Organometallic Vapor Phase Expitaxy-Grown GaN on Sapphire by Insertion of a Low-Temperature-Deposited Buffer Layer between High-Temperature-Grown GaN” Jpn.J. Appl. Phys. vol. 37 (1998) pp. 316-318.
Amano, et al., “Stress and Defect Control in GaN Using Low Temperature Interlayers” Jpn.J. Appl. Phys. vol. 37 (1998) pp. 1540-1542).
Japanese language office action and its English language translation for corresponding Japanese application No. 2003079387 lists the reference above.

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