Groundplane post-etch anodization

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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Details

29575, 156653, 156657, 1566591, 156667, 204 321, 204 381, 357 5, 357 65, 427 88, 428633, C23F 102, B44C 122, C03C 1500, C03C 2506

Patent

active

045142548

ABSTRACT:
Pinholes opened though insulating layers in Josephson integrated circuits are sealed by this post-etch anodization process. Josephson junction integrated circuits, in part, contain patterned metal films on an insulated groundplane. The patterns of conductors are created by adding a complete metal film over the insulating layers and subtractively etching to leave the desired conductor pattern. Pinholes in the underlying etch-stop insulating layer, in areas not covered by the remaining metal pattern, can be created during the subtractive etching process. Such pinholes may occur at sites made susceptible by contaminants, including flakes of process materials, which are present despite efforts to eliminate contaminants. Such pinholes provide unwanted conductive paths between the groundplane and subsequent metallization. Failures resulting from the effects of such unwanted conductive paths occur in a fashion not easily subject to identification, much less prevention. Process yields and circuit reliability are reduced. Once the integrated circuit is completed, repair is virtually impossible. This process creates seals in pinholes opened during the subtractive etching step for M2 metallization patterning, by growing niobium pentoxide specific to exposed groundplane niobium metal specific to the pinholes. The circuit wafer, after early process steps have resulted in a groundplane, insulating/spacing etch-stop layer and etched metallization pattern M2 (with possible pinholes in areas where M2 was etched away), is anodized in a medium of ammonium pentaborate dissolved in ethylene glycol for ten minutes, removed from the anodization medium, rinsed in deionized water, spun-dry and returned to the process as a pinhole-sealed intermediate process wafer at the M2 stage.

REFERENCES:
patent: 3436258 (1969-04-01), Neugebauer et al.
patent: 3784452 (1974-01-01), Martens et al.
patent: 3806430 (1974-04-01), Laibowitz et al.
patent: 3902975 (1975-09-01), Martens
Broom et al., Isolation Technique for Josephson Junction Gates, IBM Tech. Disc. Bulletin, vol. 18, No. 5, Oct. 1975, p. 1558.
Mohr et al., Eliminating Structural Surface Defects During Josephson Junction Fabrication, IBM Tech. Discl. Bull., vol. 22, No. 9, Feb. 1980, p. 4199.
Drake et al., Minimization of Excess Sub-Gap Currents in Josephson Junctions, IBM Techn. Discl. Bulletin, vol. 24, No. 2, Jul. 1981, p. 1105.
Baker et al., Reproducible Current Density Josephson Junctions, IBM Techn. Discl. Bull., vol. 24, No. 2, Jul. 1981, p. 1109.

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