Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2009-01-05
2010-06-08
Menz, Douglas M (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C438S149000, C438S479000
Reexamination Certificate
active
07732866
ABSTRACT:
Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.
REFERENCES:
patent: 5557135 (1996-09-01), Hashimoto
patent: 5959459 (1999-09-01), Satya et al.
patent: 6049109 (2000-04-01), Omura et al.
patent: 6452412 (2002-09-01), Jarvis et al.
patent: 6720779 (2004-04-01), Lee
patent: 6727501 (2004-04-01), Fan et al.
patent: 6855568 (2005-02-01), Weiner et al.
patent: 6861666 (2005-03-01), Weiner et al.
patent: 2002/0151091 (2002-10-01), Shaw et al.
patent: 2003/0071262 (2003-04-01), Weiner et al.
patent: 2003/0098706 (2003-05-01), Schroeder
patent: 2003/0234430 (2003-12-01), Friend et al.
Wang et al., “The Study and Methodology of Defects Isolation for Contacts of Non-isolated Active Regions on New Logic Designs,” ASM International, Proceedings of the 31st International Symposium for Testing and Failure Analysis, San Jose, California, Nov. 2005, pp. 479-483.
Baltzinger et al., “E-beam inspection of dislocations: product monitoring and process change validation,” IEEE Proceedings of ASMC, 2004, pp. 359-366.
Patterson et al., “Rapid Reduction of Gate-Level Electrical Defectivity using Voltage Contrast Test Structures,” Proceedings of ASMC, Mar. 2003, pp. 266-272.
Weiner et al., “Defect Management for 300 mm and 130 nm Technologies, Part 3: Another Day, Another Yield Learning Cycle,” Yield Management Solutions, 2002, pp. 15-28.
Cote William J.
Patterson Oliver D.
Brown Katherine
Hoffman Warnick LLC
International Business Machines - Corporation
Menz Douglas M
LandOfFree
Grounding front-end-of-line structures on a SOI substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Grounding front-end-of-line structures on a SOI substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Grounding front-end-of-line structures on a SOI substrate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4249179