Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-03-06
2004-07-06
Vo, Tim (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S100000, C375S257000, C375S377000
Reexamination Certificate
active
06760801
ABSTRACT:
TECHNICAL FIELD OF INVENTION
The present invention relates generally to a computer data bus, and more specifically, to a multi-drop data bus using a ground referenced voltage source input/output scheme.
BACKGROUND OF THE INVENTION
A computer system generally includes various system components coupled to one or more internal buses. Such an internal computer bus is made up of the electrical signal lines that connect the computer components. The components may include memory or multiple processors, as an example. Typically, a computer bus is based on an industry standard so computer components of various types can be designed to operate on the bus. New bus designs are often introduced which provide increased bandwidth over prior bus designs.
As processors, memories, and other components increase in speed, printed circuit board (PCB) connections that allow these components to communicate with one another behave as transmission lines. These transmission line characteristics were always present, but as edge rates increase and the transmission rates increase, the effective line lengths become longer and the transmission line effects become especially important—important to the degree that if they are not addressed, the system may not work. Reflections in the transmission line cause distortions of the signal at the receiving end of the line. These distortions can cause false triggering in clock lines, can cause erroneous information on data, address and control lines, and can contribute significantly to clock and signal jitter.
The higher speed processors are typically used on higher speed computer buses using GTL (and its variants) bus technology. For example, recent processors from Intel Corporation of Santa Clara, Calif. are designed to operate in a quad (4) processor architecture, i.e. four multiprocessors operating on a common bus. Operating at the higher computer bus speeds required impedance matching of all loads on the computer bus to ensure signal quality and integrity.
However, GTL suffers from signal integrity problems due to imperfect driver terminations, and longer settling time for reflections from terminations and stubs. GTL also has greater power supply noise due to the use of an asymmetric output driver, which only sinks current. These factors limit the data rate and the maximum number of chips sharing the multi-drop bus. Further, GTL does not provide I/O voltage compatibility between chips of different process generations. For lower V
cc
process, GTL also requires high voltage transistors for I/O to be fabricated, which requires additional process steps.
REFERENCES:
patent: 3619504 (1971-11-01), De Veer et al.
patent: 5343503 (1994-08-01), Goodrich
patent: 5638402 (1997-06-01), Osaka et al.
patent: 6434647 (2002-08-01), Bittner, Jr.
patent: 6484223 (2002-11-01), Lenz
Thomas Thomas P.
Young Ian A.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Vo Tim
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