Ground bounce reduction technique using phased outputs and...

Details Ground bounce reduction technique using phased outputs and... Ground bounce reduction technique using phased outputs and...

2001-01-19

2002-03-12

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S028000, C326S086000, C326S093000

Reexamination Certificate

active

06356100

ABSTRACT:

BACKGROUND
The disclosures herein relate generally to ground bounce caused by simultaneous switching of I/O buffers in complex integrated circuits and, more particularly, to a technique for reducing such ground bounce using phased outputs and package de-skewing for source synchronous buses.
Simultaneous switching of I/O buffers in complex integrated circuits create sudden shifts in the ground and power plane voltages. These shifts, generically referred to as “ground bounce,” cause relative shifts in the output buffers signals to the extent that a “0” can be detected as a “1” and vice versa, causing data errors. This problem is becoming increasingly troublesome due to lowered signal voltage levels and their consequent lower noise margins and the increase in density of I/O in increasingly complex chips. The worst ground bounce scenarios occur when most or all I/O buffers drive their output simultaneously.
Prior methods of addressing the above-described problem include adjusting the slew rate of individual I/O buffers, increasing the interplane capacitance using on-chip capacitors, and increasing the decoupling in the immediate region of the transmitting chip. These prior art solutions suggest the use of long phase delay periods on the order of the ground bounce resonance period, but do not include phase de-skewing and are therefore not exceedingly practical without a major revision of bus timing and protocol.
Therefore, what is needed is a technique for reducing such ground bounce using phased outputs and package de-skewing for source synchronous buses.
SUMMARY
One embodiment, accordingly, is a technique for reducing such ground bounce using phased outputs and package de-skewing for source synchronous buses. In this embodiment, the output buffers of an integrated circuit (“IC”) are phased so that half of the buffer outputs are driven first and the remaining half are driven a slight time delay later. The outputs are then de-skewed by package routing so that the earlier signals reach the package pins at the same time as the later signals. This de-skewing is accomplished by serpentining and length-matching the bank of non-delayed outputs so that these trace-induced delays match an optimized fixed clock delay used to delay the bank of delayed outputs, the traces of which are length-matched and routed as short as possible.
In an alternative embodiment, the addition of a programmable additional clock delay over and above the fixed value allows for greater phase delay values to be selected by the system designer that can then be de-skewed by additional trace length on the printed circuit board (“PCB”).
In another embodiment, the clock delay is eliminated and a similar result is achieved by delaying each data signal individually.
A principal advantage of the embodiment is that it accomplishes significant reduction in ground bounce without overlooking the necessity to perform phase de-skewing at the output of an IC.


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