Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-28
2001-11-27
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S634000, C438S640000, C438S637000, C438S638000
Reexamination Certificate
active
06323117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a grooved wiring structure in the semiconductor device and a method for forming the same.
2. Description of Related Art
In the prior art, a method has been known in which a groove type opening and a through-hole type opening are formed in an interlayer insulator film formed to cover a substrate and an underlying wiring conductor, and then filled with a metal, so that a via hole and an upper level wiring conductor are simultaneously formed. This method is disclosed in for example Japanese Patent Application Pre-examination Publication No. JP-A-63-271958, an English abstract of which is available from the Japanese Patent Office. The content of the English abstract of JP-A-63-271958 is incorporated by reference in its entirety into this application.
Now, a prior art process for the above mentioned method will be described with reference to
FIGS. 1A
to
1
F, which are diagrammatical sectional views of a portion of a semiconductor device for illustrating the prior art process in the case of forming a via hole and an upper level wiring conductor above a lower level wiring conductor, although JP-A-63-271958 discloses an example of forming a wiring conductor over an insulator layer covering a diffused layer, in electrical connection with the diffused layer through a contact hole.
As shown in
FIG. 1A
, after a first level silicon oxide film
402
is formed on a silicon substrate
401
, a first level wiring conductor A
403
is formed of for example aluminum in a predetermined shape on the first level silicon oxide film
402
, and then, a second level silicon oxide film
404
is formed to cover the whole surface.
Thereafter, as shown in
FIG. 1B
, a photoresist film
405
patterned by a conventional photolithography is formed on the second level silicon oxide film
404
, and an anisotropic etching is performed to the second level silicon oxide film
404
using the patterned photoresist film
405
as a mask, so that a through-hole type opening
420
(for a via hole) is formed to penetrate through the second level silicon oxide film
404
and to reach the first level wiring conductor A
403
.
After the photoresist
405
is removed, a second photoresist film
406
having a predetermined shape patterned by a conventional photolithography is formed on the second photoresist film
406
, and then, the second level silicon oxide film
404
is anisotropically etched using the patterned photoresist film
406
as a mask, so that groove type openings
411
and
412
for a second level wiring conductor are formed to reach an intermediate depth of the second level silicon oxide film
404
, as shown in
25
FIG.
1
C. In this process, since the through-hole type opening
420
formed in the former step is sufficiently deep, the photoresist film
406
remains at a bottom of the through-hole type opening
420
.
By removing the photoresist film
406
, a via hole
441
and groove type openings
411
and
412
are formed as shown in FIG.
1
D.
Then, a metal, for example, aluminum,
407
is deposited over the whole surface to fill the via hole
441
and the groove type openings
411
and
412
, as shown in FIG.
1
E.
Furthermore, the whole surface is etched back, so that the aluminum is caused to remain only in the via hole
441
and the groove type openings
411
and
412
, as shown in FIG.
1
F. As a result, the first level wiring conductor A
403
is connected through the aluminum filled in the via hole
441
, to a second level wiring conductor B
431
which is formed of aluminum filled in the groove type opening
411
. In addition, another second level wiring conductor C
432
is also formed of aluminum filled in the groove type opening
412
, as an independent second level wiring conductor.
FIG. 2
is a diagrammatic plan view of the prior art semiconductor device, and a sectional view taken along the line X-Y in
FIG. 2
corresponds to FIG.
1
F. In addition,
FIGS. 3A
to
3
C illustrate mask patterns used in the above mentioned photolithographic steps in the case that the photolithographic processes are a positive photoresist process.
FIG. 3A
illustrates the mask pattern for the first level wiring conductor A, and
FIG. 3B
illustrates the mask pattern of the through-hole type opening
420
for the via hole.
FIG. 3C
illustrates the mask pattern of the groove type openings
411
and
412
for the second level wiring conductors B and C.
As a technique for forming the grooved wiring conductor by filling up only an opening formed in the insulator film with a metal, the etchback process has been explained in the above mentioned prior art process. A CMP (chemical mechanical polishing) process is known as another technique. The technique for forming the grooved wiring conductor by means of the CMP process is disclosed by for example Japanese Patent Post-examination Publication No. JP-B-07-077218 corresponding to U.S. Pat. No. 4,944,836, the disclosure of which is incorporated by reference in its entirety into this application. In brief, an opening is formed in an insulator film covering a substrate, and a metal layer having a thickness sufficient to fill up the opening is deposited over the whole surface, and thereafter, the chemical mechanical polishing is conducted using a slurry comprising an acidic solution of dispersed alumina powder until a surface of the insulator film and a surface of the metal layer become substantially the same surface. If this technique is applied to a semiconductor device having a through-hole type opening and a groove type opening, there is obtained a surface more planarized in comparison with that obtained by using the etchback process.
In general, an operation speed of an integrated circuit depends upon a wiring resistance and a wiring capacitance, and therefore, it is preferred that both the wiring resistance and the wiring capacitance are low. However, in order to reduce the wiring resistance, it is necessary to enlarge the film thickness of the wiring conductor and the width of the wiring conductor. On the other hand, in order to reduce the wiring capacitance, it is necessary to narrow the width of the wiring conductor and to increase a spacing between adjacent wiring conductors.
As seen from the above, the above mentioned demands are not compatible, and therefore, it is a general practice in a circuit design to select suitable values by taking both the wiring resistance and the wiring capacitance into consideration. Namely, in a circuit having a circuit operation speed greatly depending upon the wiring resistance, it is advantageous to enlarge the film thickness and the width of the wiring conductor in order to reduce the wiring resistance. On the other hand, in a circuit having a circuit operation speed greatly depending upon the wiring capacitance, it is advantageous to narrow the width of the wiring conductor and to increase the spacing between adjacent wiring conductors in order to reduce the wiring capacitance. In both cases, however, a layout area becomes large, and therefore, the degree of integration density is sacrificed. Accordingly, it is difficult to make the circuit operation speed and the integration density compatible to each other.
In the prior art, furthermore, since the thickness of the wiring conductor is fixed, the wiring resistance and the wiring capacitance are determined directly by a circuit layout, and therefore, an optimum design cannot necessarily be realized.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which has overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a semiconductor device having an elevated circuit operation speed and an elevated integration density, by enlarging the width of selection in the wiring resistance and the wiring capacitance at the integrated circuit designing step, the
Foley & Lardner
Kang Donghee
NEC Corporation
Thomas Tom
LandOfFree
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