Grid array package with increased electrical grounding...

Details Grid array package with increased electrical grounding... Grid array package with increased electrical grounding...

2002-01-03

2003-02-04

Chauduri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S737000, C257S748000

Reexamination Certificate

active

06515362

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a grid array package, and more particularly, to a grid array package with increased electrical grounding routes and a method of fabricating the same.
2. Description of the Prior Art
Integrated circuits areused in a wide variety of electrical devices such as intelligent appliances (IA), personal computers (PC), and so on. Generally speaking, integrated circuits are enclosed inside packages to protect their fragile circuitry. The packages also function to connect integrated circuits to power, to exchange data with outside circuitry, and to ground the current of the integrated circuits. Finally, the packages are also interfaces for heat dissipation, this function becoming increasingly important for modern integrated circuits as their transistor counts and operating frequencies continue to climb. Thus, dissipation of the heat generated during the operation of integrated circuits is an important issue in designing packages.
Please refer to FIG.
1
.
FIG. 1
is a structural schematic diagram of a four-layer ball grid array package
10
for packaging an integrated circuit
12
. The package
10
comprises a substrate
14
with a top surface
11
and a bottom surface
15
. The package
10
further comprises an integrated circuit
12
mounted on the top surface
11
and four conducting layers located within the substrate
14
:a bonding pad layer
16
, a first inner conducting layer
18
, a second inner conducting layer
20
and a contact pad layer
22
. A plurality of die pads
30
disposed on the integrated circuit
12
are electrically connected to bonding ring
32
and bonding fingers
34
disposed on the top surface
11
of the substrate
14
through conducting wires
40
,
42
and
44
. The bonding rings
32
and the bonding fingers
34
are electrically connected to via holes
26
through traces
17
. The via holes
26
are electrically connected to the contact pad layer
22
, which comprises a plurality of contact pads
24
formed on the bottom surface
15
of the substrate
14
. In addition, the via holes
26
pass through the first inner conducting layer
18
and the second inner conducting layer
20
and may or may not make contact with those layers according to circuit design. To reduce the probability of an improper connection, a plurality of channels is formed in the first inner conducting layer
18
and the second conducting layer
20
and filled with a dielectric material
28
. A plurality of solder balls
36
is adhered onto the contact pads
24
for connection with outside circuitry. A route from the integrated circuit to outside circuitry runs from the die pads
30
, through the conducting wires
40
,
42
,
44
, the bonding rings
32
and bonding fingers
34
, the traces
17
, thevia holes
26
, the contact pads
24
and the solder balls
36
. The solder balls connect the package to outside circuitry.
The route for connection with outside circuitry has to pass through the first inner conducting layer
18
for grounding,and the first inner conducting layer
18
is also called a ground plane. Likewise, the second inner conducting layer
20
is also called a power plane because it is used for connecting to the power.
Please refer to FIG.
2
.
FIG. 2
is a bottom view of the package
10
. The solder balls
36
in
FIG. 2
can be divided into three groups according to their position: a center array, an intermediate group, and an outer array. The center array is composed of ground solder balls
48
for grounding. The intermediate group of contact pads comprises power solder balls
46
for providing routes to connect the package
10
to the power. The ground solder balls
48
of the center array not only provide a route for grounding but also a route for heat dissipation. If only the outer array of contact pads were present, routes from the integrated circuit
12
to the solder balls
36
would be long, and the length of the routes would affect the efficiency of heat dissipation in the package
10
. The addition of the center array of ground solder balls
48
allows redundant heat to be directly transferred to the outside circuitry.
Although the package
10
has more efficient heat dissipation, the presence of the intermediate group of contact pads causes narrow current routes. For detailed description, please refer to
FIG. 3
, which is a schematic diagram of the first inner conducting layer
18
. The first inner conducting layer
18
is also the ground plane of the package
10
. A peripheral portion
47
of the first inner conducting layer
18
comprises contact via holes
31
that electrically connect with the ground plane and intact via holes
33
that do not electrically connect with the ground plane. As discussed above, the first inner conducting layer
18
may have channels filled with dielectric materials
28
surrounding the via holes
26
. Since the power solder balls
46
surround the ground solder balls
48
and the dielectric materials
28
surrounds the via holes
26
, only a few narrow routes can be used to connect a central portion
49
of the ground plane with a peripheral portion
47
of the ground plane. This hindrance in current flow can lead to unexpected electro-magnetic interference and can further affect the operation of the integrated circuit
12
and efficiency of heat dissipation in the package
10
.
SUMMARY OF INVENTION
It is an object of the claimed invention to provide a grid array package with increased grounding routes and a method of forming the same to solve the problem of grounding plane splitting.
In accordance with the claimed invention, the grid array package includes a substrate with a top surface and a bottom surface. On the bottom surface is aninner array of contact pads where two most adjacent contact pads of the inner array of contact pads are separated by a first distance, an outer array of contact pads where two most adjacent contact pads of the outer array of contact pads are separated by a second distance, and a intermediate group of contact pads with at least one ground contact pad for grounding the grid array package. The intermediate group of contact pads is located between the inner array of contact pads and the outer array of contact pads, and is separated from the inner array of contact pads by a third distance and from the outer array of contact pads by a fourth distance. The third distance and the fourth distance are greater than the first distance and the second distance.
It is an advantage of the claimed invention that the package has an increased number of grounding routes to improve the efficiency of heat dissipation.


REFERENCES:
patent: 5703402 (1997-12-01), Chu et al.

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