Grid array microelectronic packages with increased periphery

Details Grid array microelectronic packages with increased periphery Grid array microelectronic packages with increased periphery

2005-08-16

2005-08-16

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S773000, C257S737000, C257S738000, C257S780000, C257S692000

Reexamination Certificate

active

06930400

ABSTRACT:
A grid array microelectronic package includes a substrate and an array of external connectors on the substrate that are arranged in rows and columns to define a periphery of the array and the interior of the array. A routing channel is provided in the array that increases the periphery of the array by at least four external connectors, compared to absence of the routing channel. The routing channel may be made of two missing external connectors, at least two strapped external connectors and/or at least two “no-connect” external connectors in the array that extend from the periphery of the array towards the interior of the array. Signal conductors may extend along the routing channel.

REFERENCES:
patent: 4852016 (1989-07-01), McGehee
patent: 5269453 (1993-12-01), Melton et al.
patent: 5773882 (1998-06-01), Iwasaki
patent: 5796169 (1998-08-01), Dockerty et al.
patent: 5814890 (1998-09-01), Iwasaki
patent: 5859474 (1999-01-01), Dordi
patent: 6001661 (1999-12-01), McBean, Sr.
patent: 6677677 (2004-01-01), Kimura et al.
Rōrgren,Chapter E: Ball Grid Array Technology, The Nordic Electronics Packaging Guideline, 2000, 5 pp.
Horiuchi et al.,Escape Routing Design to Reduce the Number of Layers in Area Array Packaging, IEEE Transactions on Advanced Packing, vol. 23, No. 4, Nov. 2000, pp. 686-691.
Betz et al.,Effect of the Prefabricated Routing Track Distribution of FPGA Area-Efficiency, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, No. 3, Sep. 1998, pp. 445-456.
Wakabayashi et al.,An Optimal Pin Assignment Algorithm With Improvement of Cell Placement in Standard Cell Layout, Proceedings of IEEE Asia Pacific Conference on Circuits and Systems '96, Nov. 18-21, 1996, pp. 381-384.
Greenberg et al.,Single-Layer Channel Routing and Placement with Single-Sided Nets, Computers Math. Applic., vol. 32, No. 4, 1997, pp. 1-7.
Chen et al.,A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, No. 8, Aug. 1995, pp. 1030-1037.
Li et al.,Global Routing for Gate Array, IEEE Transactions on Computer-Aided Design, vol. CAD-3, No. 4, Oct. 1984, pp. 298-307.

Affiliated with

Also associated with

Rating

Grid array microelectronic packages with increased periphery does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Grid array microelectronic packages with increased periphery, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Grid array microelectronic packages with increased periphery will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3516626