Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate
2001-05-04
2002-12-10
Graybill, David E. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With bumps on ends of lead fingers to connect to semiconductor
C257S676000
Reexamination Certificate
active
06492713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to maintaining the structure of viscous materials applied to semiconductor components. More particularly, the present invention relates to inverting electrical components formed from viscous materials or which include viscous materials in order to maintain the material boundary definition during baking, curing, and/or drying.
2. State of the Art
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are goals of the computer industry. As components become smaller and smaller, tolerances for all semiconductor structures (circuitry traces, printed circuit board and flip chip bumps, adhesive structures for lead attachment, encapsulation structures, and the like) become more and more stringent. However, because of the characteristics of the materials (generally viscous materials) used in forming the semiconductor structures, it is becoming difficult to form smaller circuitry traces, conductive polymer bumps with closer pitches, adequate adhesive structures for leads attachment, and adequate encapsulation structures.
U.S. Pat. No. 5,286,679 issued Feb. 15, 1994 to Farnworth et al. (“the '679 patent”), assigned to the assignee of the present invention and hereby incorporated herein by reference, teaches attaching leads to a semiconductor device with adhesive in a “lead-over-chip” (“LOC”) configuration. The '679 patent teaches applying a patterned thermoplastic or thermoset adhesive layer to a semiconductor wafer. The adhesive layer is patterned to keep the “streets” on the semiconductor wafer clear of adhesive for saw cutting and to keep the wire bonding pads on the individual dice clear of adhesive for wire bonding. Patterning of the adhesive layer is generally accomplished by hot or cold screen/stencil printing or dispensing by roll-on. Following the printing and baking of the adhesive layer on the semiconductor wafer, the individual dice are singulated from the semiconductor wafer. During packaging, each adhesive coated die is attached to leadfingers of a lead frame by heating the adhesive layer and pressing the leadfingers onto the adhesive. If the adhesive layer is formed of a thermoset material, a separate oven cure is required. Furthermore, the adhesive layer may be formulated to function as an additional passivating/insulating layer or alpha barrier for protecting the packaged die.
Although the teaching of the '679 patent is a substantial advancement over previous methods for attaching leads in a LOC configuration, the miniaturization of the circuitry makes it difficult to achieve an adequate profile on the adhesive, such that there is sufficient area on the top of the adhesive to attach the leadfingers. The process disclosed in the '679 patent is illustrated in
FIGS. 23-29
.
FIG. 23
illustrates a side, cross-sectional view of a semiconductor substrate
602
with a bond pad
604
, wherein a stencil or a screen print template
606
has been placed over the semiconductor substrate
602
. The semiconductor substrate
602
is generally a wafer, although the term as used herein is not so restricted, and other substrate structures including silicon-on-insulator (“SOI”) and printed circuit boards (“PCB”) are specifically included. The stencil or screen print template
606
is patterned to clear the area around the bond pads
604
and to clear street areas
608
for saw cutting (i.e., for singulating the substrate into individual dice). An adhesive material
610
is applied to the stencil or screen print template
606
, as shown in FIG.
24
. Ideally, when the stencil or screen print template
606
is removed, adhesive prints
612
are formed with vertical sidewalls
614
and an adhesive material upper surface
616
, as shown in FIG.
25
. However, since the adhesive material
610
must have sufficiently low viscosity to flow and fill the stencil or screen print template
606
, as well as allow for the removal of the stencil or screen print template
606
without the adhesive material
610
sticking thereto, the adhesive material
610
of the adhesive prints
612
will spread, sag, or flow laterally under the force of gravity after the removal of the stencil or screen print template
606
, as shown in FIG.
26
. This post-application flow of adhesive material
610
can potentially cover all or a portion of the bond pads
604
or interfere with the singulating of the semiconductor wafer by flowing into the street areas
608
.
Furthermore, and of even greater potential consequence than bond pad or street interference is the effect that the lateral flow or spread of adhesive material
610
has on the adhesive material upper surface
616
. As shown in
FIG. 27
, the adhesive material upper surface
616
is the contact area for leadfingers
618
of a lead frame
620
. The gravity-induced flow of the adhesive material
610
causes the once relatively well-defined edges
622
of the adhesive material to curve, resulting in a loss of surface area
624
(ideal shape shown in shadow) for the leadfingers
618
to attach. This loss of surface area
624
is particularly problematical for the adhesive material upper surface
616
at the adhesive material end
626
thereof. At the adhesive material end
626
, the adhesive material flows in three directions (to both sides as well as longitudinally), causing a severe curvature
628
, as shown in
FIGS. 28 and 29
. Stated are three ways the longitudinal ends of the adhesive print on patch flow in a 180E° flow front, resulting in blurring of the print boundaries into a curved perimeter. This curvature
628
results in complete or near complete loss of effective surface area on the adhesive material upper surface
616
for adhering the outermost leadfinger closest to the adhesive material end
626
(leadfinger
630
). This results in what is known as a “dangling lead.” Since the leadfinger
630
is not adequately attached to the adhesive material end
626
, the leadfinger
630
will move or bounce when a wirebonding apparatus (not shown) attempts to attach a bond wire (not shown) between the leadfinger
630
and its respective bond pad
604
(shown from the side in FIG.
28
). This movement can cause inadequate bonding or non-bonding between the bond wire and the leadfinger
630
, resulting in the failure of the component due to a defective electrical connection.
LOC attachment can also be achieved by placing adhesive material on the leadfingers of the lead frame rather than on the semiconductor substrate. The adhesive material
702
is generally spray applied on an attachment surface
704
of leadfingers
706
, as shown in FIG.
30
. However, the viscous nature of the adhesive material
702
results in the adhesive material
702
flowing down the sides
708
of the leadfinger
706
and collecting on the reverse, bond wire surface
710
of the leadfinger
706
, as shown in FIG.
31
. The adhesive material
702
, which collects and cures on the bond wire surface
710
, interferes with subsequent wirebonding which can result in a failure of the semiconductor component. The flow of adhesive material
702
from the attachment surface
704
to the bond wire surface
710
can be exacerbated if the leadfingers
706
are formed by a stamping process, rather than by etching, the other widely employed alternative. The stamping process leaves a slight curvature
712
to edges
714
of at least one surface of the leadfinger
706
, as shown in FIG.
32
. If an edge curvature
712
is proximate the leadfinger attachment surface
704
, the edge curvature
712
results in less resistance (i.e., less surface tension) to the flow of the adhesive material
702
. This, of course, results in the potential for a greater amount of adhesive material
702
to flow to the bond wire surface
710
.
Material flow problems also exist in application of encapsulation materials. After a semiconductor device is attached to a printed circuit board (“PCB”) by any known chip-on-board (“COB”) technique, the semico
Ahmad Syed S.
Jiang Tongbi
Graybill David E.
Micro)n Technology, Inc.
Traskbritt
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