Graphics user interface for power optimization diagnostics

Details Graphics user interface for power optimization diagnostics Graphics user interface for power optimization diagnostics

1999-12-15

2003-04-22

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S322000, C713S324000

Reexamination Certificate

active

06553502

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to debugger and dis-assembly methods, and more particularly to tools directed to providing programming that reduces the power consumption of a processor.
BACKGROUND OF THE INVENTION
Power efficiency for processor-based equipment is becoming increasingly important as people are becoming more attuned to energy conservation issues. Specific considerations are the reduction of thermal effects and operating costs. Also, apart from energy conservation, power efficiency is a concern for battery-operated processor-based equipment, where it is desired to minimize battery size so that the equipment can be made small and lightweight. The “processor-based equipment” can be either equipment designed especially for general computing or equipment having an embedded processor.
From the standpoint of processor design, a number of techniques have been used to reduce power usage. These techniques can be grouped as two basic strategies. First, the processor's circuitry can be designed to use less power. Second, the processor can be designed in a manner that permits power usage to be managed.
On the other hand, given a particular processor design, its programming can be optimized for reduced power consumption. Thus, from a programmer's standpoint, there is often more than one way to program a processor to perform the same function. For example, algorithms written in high level programming languages can be optimized for efficiency in terms of time and power. Until recently, at the assembly language level, most optimization techniques have been primarily focussed on speed of execution without particular regard to power use.
The programmer's task of providing power efficient code can be performed manually or with the aid of an automated code analysis tool. Such a tool might analyze a given program so to provide the programmer with information about its power usage information. Other such tools might actually assist the programmer in generating optimized code.
U.S. Pat. No. 5,557,557, to Franz, et al., entitled “Processor Power Profiler”, assigned to Texas Instruments Incorporated, describes a method of modeling power usage during program execution. A power profiler program analyzes the program and provides the programmer with information about energy consumption. A power profiler is also described in U.S. Pat. No. 6,125,334, to L. Hurd, entitled “Module-Configurable, Full-Chip Power Profiler”, assigned to Texas Instruments Incorporated.
SUMMARY OF THE INVENTION
One aspect of the invention is a computer-implemented method of providing a visualization of power usage of a computer program. The method is especially suited for use as part of a debugging process, for use by a computer programmer. First, a determination is made of power usage per processor cycle as the code executes. This determination may be made by receiving values from a power measurement process, from some sort of modeling or estimation process, or from some other means of determining power usage. The section of computer code corresponding to each cycle is displayed. Also, power usage per cycle is displayed as a graph, such that each section of code is displayed with a corresponding graphical measure of power usage.
An advantage of the invention is that it provides a programmer with a visualization of cycle-by-cycle power dissipation. Power usage values and graphical representations are displayed together with corresponding sections of code, so that the programmer can easily access the code to make modifications to reduce power dissipation.


REFERENCES:
patent: 5557557 (1996-09-01), Frantz et al.
patent: 5941991 (1999-08-01), Kageshima
patent: 6338025 (2002-01-01), Bowen et al.
A. Parikh et al., VLIW Scheduling for Energy and Performance, IEEE, Date 2001, p. 111 to 117.*
M. Toburen and T. Conte, Instruction Scheduling for Low Power Dissipation in High Performnace Microprocessors, The Power Driven Micro-architecture Workshop, Barcelona, Spain, Jun. 1998.

Affiliated with

Also associated with

Rating

Graphics user interface for power optimization diagnostics does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Graphics user interface for power optimization diagnostics, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Graphics user interface for power optimization diagnostics will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3094898