Computer graphics processing and selective visual display system – Computer graphics display memory system – First in first out
Reexamination Certificate
1999-03-03
2002-07-02
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
First in first out
C345S564000, C345S537000, C710S055000
Reexamination Certificate
active
06414689
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to computer systems, and more particularly relates to graphics engine interface.
BACKGROUND OF THE INVENTION
With the advances of semiconductor and computer technology, computer systems are becoming faster and at the same time smaller in size. Desktop and even laptop computer systems now possess processing speeds of mainframe computers that used to fill up a small room. Even hand-held computer systems such as personal digital assistants (PDA), which are becoming more popular, are getting more powerful. As computer systems become more miniaturized and inexpensive, more demands are constantly being required of them as well. One such demand is speed or performance.
As computer systems become more powerful and more miniaturized, power-conservation also presents a difficult challenge to overcome. Because of their small size, hand-held computer systems are powered by battery which have limited operating duration. Since more power is required for faster and more powerful processors, innovative solutions are required to conserve power and thereby extend the battery operating duration.
To increase the speed of computer systems, a decentralized approach has been implemented in their design. Within each computer system there are many integrated circuits (IC) designed to perform dedicated functions such as a memory controller, a hard disk controller, a graphics/video controller, a communications controller, and other peripheral controllers. These dedicated integrated circuits can simultaneously perform the different functions independently. Such decentralized approach minimizes
bottlenecks
and therefore helps improve the speed of computer systems.
Even so, the tasks performed by computer systems are becoming increasingly more complex. This is particularly true in the area of computer graphics. Computer systems are now capable of generating complex and high-resolution 3 dimensional (3D) graphics objects with lifelike movements. These 3D graphics objects require a great deal of data transfer (e.g., retrieving the attributes data related to the object such as data block height, width, color, and texture from system memory) and processing (e.g., computing the color and texture values for the object's pixels to accurately reflect the object's shading at a position) These 3D graphics objects also require a great deal of power to generate. For these reasons, on-going efforts are being made to constantly improve power conservation and performance in the area of computer graphics.
Generally, in a graphics computer system, computer graphics objects are first constructed with combinations of graphics primitives using a graphics application program. The graphics primitives are connected together to form a geometrical model of the desired graphics object or picture to be displayed on the monitor. The graphics model is a linked data structure that contains a detailed geometric description of the graphics object and its associated attributes (e.g., color, shading, texture, lighting, etc.) describing how the object should appear. Data related to the graphics model are stored in the computer system memory. On the other hand, data ready to be displayed on the monitor is stored as a pixmap in a frame buffer (i.e., a pixel pattern mapped into the frame buffer). In response to a user graphics command (e.g., a Raster Operation (ROP)), graphics data from the system memory and from the frame buffer are retrieved with the help of the Central Processor (CPU) and the Memory Interface Unit (MUI) and provided to the Graphics Engine (GE) for processing. The processed data is then provided with the help of the MIU to the frame buffer for subsequent display by the monitor.
In transferring data from/to the system memory and the frame buffer, First-In-First-Out (FIFO) buffers may be used so that the CPU, MIU, and GE can operate asynchronously thereby allowing these units to reach their maximum performance. However, when the GE provides the processed data to the frame buffer, an address is traditionally provided to indicate the location in the frame buffer where the processed data is to be stored. Because the associated address may require between 16-21 bits thereby increasing the required size of the FIFO buffer. Such a large FIFO buffer requires added gates which means increased costs as well as increased power consumption. Moreover, the traditional approach also means that the GE is primarily responsible for computing the address which slows down the processing speed and increases the power consumption of the GE.
Thus, a need exists for an apparatus, system, and method for passing address information in a GE FIFO architecture using a reduced-sized FIFO buffer while improving the processing speed and decreases the power consumption of the GE.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an apparatus, system, and method for passing address information in a Graphics Engine (GE) FIFO interface architecture using a reduced-sized FIFO buffer while improving the processing speed and decreases the power consumption of the GE. Under the present invention, the GE interfaces with all the external blocks through the FIFO interface thereby allowing the GE's clock to run asynchronously with other blocks.
The present invention meets the above need with a First-In-First-Out (FIFO) interface apparatus that is coupled to a Central Processing Unit (CPU), a Graphics Engine (GE), and a frame buffer. The FIFO interface apparatus comprises a write FIFO buffer coupled between the GE and the frame buffer. The write FIFO buffer is used for transferring data packets generated by the GE to the frame buffer wherein each data packet includes a predetermined number of data bits processed by the GE, a first address flag bit, and a second address flag bit. The first and second address flag bits are used to determine a next write address in the frame buffer for storing the predetermined data bits from an immediately subsequent data packet. More particularly, the first address flag bit indicates whether the predetermined number of data bytes in each data packet is to be added to a present write address to determine the next write address. The second address flag bit indicates whether a stride is to be added to an updated starting write address to determine the next write address. A stride is defined as the number of bytes between the first pixel of one scan line to the first pixel of the next scan line.
The FIFO interface apparatus may further comprises a line draw FIFO buffer coupled to a line draw engine, which in turn is connected to the GE, and the frame buffer. The line draw FIFO buffer is used in transferring the first and second address flag bits from the line draw engine to the frame buffer. The first and second address flag bits are used to determine a next read address in the frame buffer for retrieving data stored in the read address of the frame buffer. In particular, the first address flag bit indicates whether the predetermined number of data bytes in each data packet is to be added to a present read address to determine the next read address. The second address flag bit indicates whether a stride is to be added to the present read address to determine the next read address. A stride is defined as the number of bytes between the first pixel of one scan line to the first pixel of the next scan line.
All the features and advantages of the present invention will become apparent from the following detailed description of its preferred embodiment whose description should be taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5027326 (1991-06-01), Jones
patent: 5295240 (1994-03-01), Kajimoto
patent: 5557733 (1996-09-01), Hicok et al.
patent: 5577203 (1996-11-01), Reinert et al.
patent: 5745791 (1998-04-01), Peek et al.
patent: 5777629 (1998-07-01), Baldwin
Mediaq Inc.
Nguyen & Associates
Tung Kee M.
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