Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output addressing
Reexamination Certificate
2002-05-09
2003-09-09
Gaffin, Jeffrey (Department: 2185)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output addressing
C710S056000, C711S202000, C711S203000
Reexamination Certificate
active
06618770
ABSTRACT:
COPYRIGHT NOTICE
Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to bus protocol bridging. More particularly, the invention relates to input/output (I/O) address translation, such as remapping a continuous logical address space to a potentially discontinuous physical address space, in a bridge.
2. Description of the Related Art
Input/output (I/O) peripheral devices typically operate more efficiently if they are presented with a large contiguous view of system memory (main memory). This allows such devices to make random accesses into a large area of memory containing the data in which they are interested. A contiguous view of memory is especially important for graphics cards which must often retrieve an entire texture map in order to render a scene on a display device. For purposes of this application, the address space in which the I/O peripheral device operates that gives the perception of a large contiguous address space is called a “virtual address space.”
At any rate, because the peripheral device employs a different address space than the main memory of the host computer system, a process called “address translation” is required to map the virtual addresses supplied by the peripheral device to the corresponding potentially discontinuous physical addresses in main memory.
An example of a current technique for address translation will now be described with reference to FIG.
1
.
FIG. 1
is a high-level block diagram of a general purpose computer system
100
that illustrates translation of graphics addresses to physical addresses. The computer system
100
includes processing means, such as one or more processors
105
and
110
, a chipset
120
, a main memory
125
, a memory bus
124
, an Accelerated Graphics Port (AGP) bus
130
, and a PCI bus
140
. In this example, the main memory includes a graphics address relocation table (GART) which contains entries for mapping virtual addresses used by a peripheral device, such as graphics accelerator
135
, to physical addresses in main memory
125
.
The chipset
120
provides bridging functions between the AGP bus
130
, the PCI bus
140
, and the memory bus
124
. As part of the bridging function, the chipset
120
translates graphics addresses contained in inbound read and write transactions (e.g., read and write transactions originated by the graphics accelerator
135
) to corresponding physical addresses in main memory
125
using the GART
126
. Consequently, in a computer system configured in accordance with
FIG. 1
, processing of graphics data, such as texture maps, requires multiple accesses to main memory
125
. First, the chipset
120
must retrieve an entry from the GART
126
that corresponds to the graphics address specified in the transaction being executed. Then, after the desired physical address has been determined by the chipset
120
, the chipset
120
must perform a second access to main memory
125
in order to read or write the data specified by the transaction.
One of the great advantages of AGP is that it isolates the video subsystem from the rest of the computer system so there isn't nearly as much contention over I/O bandwidth as there is with PCI. However, from the description above, it should be apparent that there are a number of inefficiencies associated with the way translation of AGP transactions are currently handled. First, accesses to main memory
125
, which is typically made up of dynamic random access memories (DRAMs), are relatively slow compared to accesses to static random access memory (SRAM), for example. Second, the main memory
125
accesses for purposes of address translation must compete with other access requests, such as those originated by processor
105
or
110
and received over the system bus
115
or those received on the PCI bus
140
. As a result, AGP translations are slowed down by competing traffic. Finally, if the translation unit (not shown) handles multiple types of traffic, e.g., system bus traffic, PCI traffic, and AGP traffic, the situation is further complicated as arbitration logic becomes necessary to resolve contention for the translation unit among the various types of inbound and outbound transactions.
It would be desirable, therefore, to provide a technique for translating I/O addresses that speeds up the execution of I/O transactions and offers a simplified implementation of the address translation logic. In addition, it would be advantageous to perform the necessary I/O address translation in a device that is insulated from other types of traffic, such as system bus traffic or traffic from other I/O devices.
BRIEF SUMMARY OF THE INVENTION
A method and apparatus are described for performing address translation in an input/output (I/O) expansion bridge. The I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit. The first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports. The first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system. The second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device. The address translation unit is coupled to the first interface unit and the second interface unit. The address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.
Other features and advantages of the invention will be apparent from the accompanying drawings and from the detailed description.
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Intel Corporation, “Intel 440GX AGPset Product Overview”, downloaded from website, http://developer.intel.com/design/chipsets/440gx on Nov. 16, 1999, 3 pps.
Intel Corporation, “Intel 440GX AGPset: 82443GX Host Bridge/Controller Datasheet”, Jun. 1998, title page through p. 1-3 and pp. 4-1 through 4-10.
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Cross Leonard W.
Moran Douglas R.
Nayyar Raman
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