Graphical loop profile analysis

Details Graphical loop profile analysis Graphical loop profile analysis

2007-01-23

2007-01-23

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C703S013000, C703S014000

Reexamination Certificate

active

10126913

ABSTRACT:
A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.

REFERENCES:
patent: 6233540 (2001-05-01), Schaumont et al.
patent: 6606588 (2003-08-01), Schaumont et al.
patent: 6701501 (2004-03-01), Waters et al.
patent: 2003/0131325 (2003-07-01), Schubert et al.
Lakshminarayana et al., “Wavesched: a novel scheduling technique for control-flow intensive designs”, May 1999 , Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol. 18 , Issue: 5 , pp. 505-523.
Ching-Yi et al., “High-level DSP synthesis using concurrent transformations, scheduling, and allocation”, Mar. 1995, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol. 14, Issue: 3 , pp. 274-295.
Liu et al., “Loop optimization for aggregate array computations”, May 14-16, 1998 , Computer Languages, 1998. Proceedings. 1998 International Conference on , pp. 262-271.
Ravi et al., “Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions”, Nov. 8-12, 1998,Computer-Aided Design, ICCAD, Digest of Technical Papers. IEEE/ACM International Conference on, pp. 244-250□□.
Bhattacharya et al., “Performance analysis and optimization of schedules for conditional and loop-intensive specifications”, 1994, Annual ACM IEEE Design Automation Conference 31st annual conference on Design automation, pp. 491-496.
U.S. Appl. No. 09/839,376, filed Apr. 20, 2001, Prakash et al.
U.S. Appl. No. 09/919,650, filed Jul. 31, 2001, Gutberlet et al.
U.S. Appl. No. 09/957,442, filed Sep. 18, 2001, Waters et al.
U.S. Appl. No. 60/362,679, filed Mar. 8, 2002, Prakash et al.
U.S. Appl. No. 10/126,911, filed Apr. 19, 2002, Burnette et al.
“Loops”,Understanding Behavioral Synthesis(A Practical Guide to High-Level Design), by John P. Elliott, Chapter 6, pp. 77-103 (1999).
“Pipelining”,Understanding Behavioral Synthesis(A Practical Guide to High-Level Design), by John P. Elliott, Chapter 8, pp. 137-154 (1999).

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