Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1996-11-04
2001-04-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06212666
ABSTRACT:
FIELD OF THE INVENTION
This application relates to a method and apparatus for designing and debugging circuits and, particularly, to a method and apparatus for analyzing and debugging timing information of digital circuits.
BACKGROUND OF THE INVENTION
In recent years, human circuit designers have more trouble understanding and debugging the circuits they design. A first reason is that circuits are becoming larger and more complex. As circuit size increases, it becomes harder for a human being to keep all portions of the circuit in his mind at once. Even a moderate sized circuit of a few thousand gates contain tens or hundreds of millions of paths between the gates.
Another reason for increasing circuit complexity is that circuit designers often design the circuit at a functional level, using a Hardware Description Language (“HDL”) such as VHDL or Verilog. The HDL code is then translated into an internal representation of a circuit in the memory of a computer. Once an internal circuit representation exists, the circuit designer tests the circuit representation to determine whether the circuit is acceptable. If the circuit is not acceptable, the designer will change the HDL description until an acceptable circuit is obtained.
An important criteria in determining whether a circuit is acceptable is whether the circuit meets its timing constraints. The time required for a signal to pass between circuit elements is called “delay.” A circuit does not meet its timing constraints when some of the paths through the circuit have too long a delay.
As discussed above, even a moderate sized circuit having a few thousand gates can have tens or hundreds of millions of paths.
Therefore, it is not uncommon for a circuit to have many thousands of paths with delays that are too long. Of course, the existence of thousands of long paths does not necessarily mean that thousands of changes need to be made to the circuit. Often, one change to the circuit, such as moving an operation from one cycle to another, performing operations in parallel instead of serially, or using a faster implementation of a sub-function, will fix a timing problem.
Unfortunately, conventional timing analyzer CAD tools do not make it easy to identify the relationships between long paths. Therefore, it is often difficult to identify the parts of a circuit that need to be changed in order to eliminate long paths. Conventional software tools do not identify the parts of the circuit that participate in a large number of long paths. If the circuit was specified at the functional level, this problem is especially difficult, because it is not always easy to identify which parts of the functional description generate which paths of the circuit. Because conventional tools make it difficult to find which parts of the circuit participate in many long paths, designers often resort to fixing the long paths identified by the timing analysis CAD tool, only to find that the next run of the tool finds a new set of long paths that are only slightly shorter than the paths just fixed. Without the ability to find parts of the circuit that participate in many long paths, the designer is forced into many iterations of fixing paths and then rerunning the conventional CAD tool to find the next longest paths.
The following paragraphs provide a detailed description of a typical design process performed by a circuit designer and are provided as an aid to understanding the circuit design process. When designing a circuit, a human designer first conceives of a particular function to implement, as well as constraints such as timing or area that the implementation must meet. Next, the designer mentally transforms the desired function into a high level generic technology (Gtech) circuit including components such as gates, adders, and registers.
The designer then chooses a technology provided by a semiconductor vendor from which the circuit components will be chosen. The process of choosing circuit components from a specific technology is called mapping; mapping creates a “mapped circuit.” To map a circuit, the designer draws a schematic of a mapped circuit that implements the desired function with a CAD schematic capture tool. The mapped circuit includes parts from a software representation of a specific technology library which is supplied by a silicon vendor. The schematic shows how more primitive functional elements, such as gates or transistors, connect together to form more sophisticated functions such as arithmetic logic units. In addition, modem schematic capture tools allow the designer to divide the design hierarchically into interconnected pieces, and then allow the user to specify the details of each of the pieces separately. For example, Design Architect by Mentor Graphics of Wilsonville, Oreg. provides these schematic capture functions.
Conventional CAD tools, such as those indicated above, can then take the connections in the schematic and other information to evaluate the mapped circuit and to specify the tooling necessary to construct the circuit. Such tools evaluate the mapped circuit in many ways. For example, commercial CAD tools often have a simulator that predicts the response of the mapped circuit to designer specified input patterns. QuickSim II by Mentor Graphics of Wilsonville, Oreg. is a commonly used simulator. Another common CAD tool is a path delay analyzer that identifies the longest timing path in a mapped circuit design. DesignTime by Synopsys, Inc. of Mountain View, Calif. is a tool that provides path delay analysis.
Alternately, designers can design circuits using a synthesis method. In synthesis, the designer describes the desired function using VHDL, Verilog, or any other synthesis source language, to specify the behavior. This allows the designer to specify the digital circuit at a higher level and allows the CAD tools to assist the designer in defining the functionality of the digital circuit. A software translator then converts that description into generic technology structures that directly correspond statement by statement with the designer's description. Mapping replaces the generic technology structures with structures from a specific technology library. Technology libraries are provided by silicon vendors to specify the types of parts which the vendor can manufacture. Technology libraries include specific information regarding the functionality and physical characteristics such as area and delay of gates which can be built by the silicon vendor. Technology libraries are designed to work with synthesis systems. A synthesis system can use a technology library to choose available gates from which the silicon vendor can fabricate the digital circuit. Because synthesis enables the designer to look at higher levels of abstraction, circuits tend to be even larger than circuits developed without synthesis tools.
As discussed above, conventional CAD tools allow a designer to examine only a single discrete path in the circuit at a time. This is problematic and leads to an iterative design process in which the designer repeatedly changes a circuit to shorten the longest path. Furthermore, because synthesized circuits can be very large, it becomes problematic to fix problems involving timing delays in synthesized circuits.
SUMMARY OF THE INVENTION
A preferred embodiment of the present invention overcomes the problems and disadvantages of the prior art by displaying a “delay chart” of a circuit on a display screen using a variety of user-selected formats. These formats include right-to-left, left-to-right, merged (in which duplicative paths are merged together), and elimination of zero length paths. A delay chart graphically represents the paths in a circuit so that the length of a path on the display corresponds directly to the path delay. Thus, paths with long delays will be displayed as longer than paths with short delays.
The described embodiment also allows the designer to select various parts of the delay chart and then automatically highlights related portions of the HDL code (which also is displayed on the display
Donelly Ross A.
Gohl Karl W.
Hissen Helmut
Brown & Raysman Millstein Felder & Steiner LLP
Siek Vuthe
Smith Matthew
Synopsys Inc.
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