Graphic RAM having a dual port and a serial data access method t

Details Graphic RAM having a dual port and a serial data access method t Graphic RAM having a dual port and a serial data access method t

1995-01-26

1998-06-02

Lee, Michael H.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345508, 395510, G09G 536

Patent

active

057607915

ABSTRACT:
A graphic RAM array has a plurality of sub blocks which share random and serial output paths. This structure enables random access to the random output path of one RAM array while a specific sub block of another other RAM array is performing a display operation via the serial output path. The graphic RAM does not have a separate data register and outputs the serial data using only the RAM array. Thus, only the RAM array is formed in the cell core region, thereby reducing the size and price of the chip. In addition, it is possible for the graphic RAM to be compatible with a system having a conventional video RAM controller.

REFERENCES:
patent: 4747081 (1988-05-01), Heilveil et al.
patent: 4937781 (1990-06-01), Lee et al.
patent: 5343425 (1994-08-01), Saito et al.
patent: 5367486 (1994-11-01), Mori et al.
patent: 5519413 (1996-05-01), Thomas et al.
patent: 5523979 (1996-06-01), Nemazie
patent: 5543824 (1996-08-01), Priem et al.

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