Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
1997-08-29
2002-08-06
Tung, Kee M. (Department: 2776)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S505000, C345S213000
Reexamination Certificate
active
06429871
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a graphic processing apparatus for displaying and printing out characters and graphics, and in particular, to a graphic processing apparatus capable of effecting a drawing processing at a high speed not only in a frame buffer but also in a system memory (main memory).
There has been a method (called a bit map method) to display characters and graphics on a CRT screen according to a raster scan method by use of a memory (bit map memory) storing information associated with each pixel of the display apparatus. Furthermore, this method including the bit map memory has also been applied to a case where control is effected to output data to a printer. Conventionally, processing to generate characters and graphic data in the bit map memory is primarily achieved by means of the software; however, there has arisen a problem that the processing speed is low because of a great amount of data to be processed. On the other hand, particularly, in a field where graphic forms are to be generated at a high speed, there has been partly used a method including dedicated hardware, which is however attended with a disadvantage that the cost of the graphic processing apparatus is increased.
To cope with such a situation, the function to generate characters and graphic data has become to be integrated in an LSI chip. Such an LSI has been proposed in the “CRT Controller Having a Plenty of Commands Such As Paint Out and Copy and Enabling to Specify Drawing Position by Coordinates” written by Kazuo Minorikawa in the “Nikkei Electronics”, May 21, 1984, pp. 221-254; and in the U.S. Ser. Nos. 686,039 and 727,850. This LSI enables to greatly increase the speed of the graphic processing at a relatively low cost.
According to the paper above, the drawing processing can be executed in a frame buffer at a high speed; however, the drawing processing cannot be achieved in a system memory (main memory) connected to a CPU.
For example, other output means such as a control circuit of a printer is connected to a system bus in many cases, where a buffer for use with a print operation is reserved in the system memory. At the present stage of technology, in the case where graphic data is to be outputted to a printer, since the drawing operation cannot be accomplished by the CRT controller above, the drawing is effected by the software. As a result, though the graphic data to be displayed in the CRT screen is drawn at a high speed, the drawing of the graphic data to be outputted to a printer is executed at a low speed.
On the other hand, it can be considered as means to improve the processing performance, to subdivide the frame buffer in color plane units, thereby effecting a concurrent processing by use of a plurality of graphic processors. According to the method described in the papers above using the CRT controller, in order to achieve a copy processing of the same fundamental information (for example, font data of a character) onto a plurality of planes, it is necessary to before-hand store fundamental information in the frame buffer corresponding to the respective planes. Namely, the memory utilization efficiency is lowered because same information is arranged in a plurality of memories.
According to the prior art technology as described above, in addition to the low speed of the drawing operation in the system memory, a plurality of same information such as a character font must be provided in the case where the frame buffer is subdivided into color plane units to achieve a parallel processing thereon by a plurality of processors.
The JP-A-60-136793 has disclosed a graphic processing apparatus including a graphic generate function implemented as an LSI to achieve a graphic processing at a high speed by use of a bit map method. In the JP-A-60-136793, a plurality of pixel information are stored in a word of a memory, a predetermined word is read from the memory while an address identifying a pixel in sequence is being generated, particular pixel data is updated in the word, and the word data thus attained is written again in the word, thereby effecting a drawing operation. That is, the processing of a word is effected through a sequence of processing of a read operation, an arithmetic operation, and a write operation so as to achieve a drawing operation.
Furthermore, the JP-A-60-40588 describes a technology to write pixel information of a bit in a raster direction.
The JP-A-61-130991 (Japanese Patent Application No. 59-251907) has disclosed a graphic processing apparatus in which X and Y coordinates are calculated so as to effect a drawing operation while calculating an X-coordinate memory address corresponding to the attained coordinate values. According to the known example, the arithmetic unit to execute the coordinate calculation and an arithmetic unit to achieve the memory address calculation are controlled by a common microprogram.
In the “LSI Handbood”, OHM-Sha, Ltd., Nov. 30, 1984, page 556 and subsequent pages, there has been disclosed a method in which in consideration of the fact that when a relatively complex processing is required to be executed in a unit of a pixel like in a graphics processing, it is not necessarily advantageous in the improvement of the utilization efficiency of the processor and in the enhancement of the speed of the image processing to accomplish all processing by the microprocessor, the generation of basic graphic forms, the operation to paint out a graphic form, the drawing of lines, etc. are achieved by an apparatus such as a display controller dedicated to the image processing.
Incidentally, when a bold line is to be drawn by a line drawing command in the prior art image processing apparatus such as a display controller, a line having a width determined by a size of a pixel is required to be many times drawn to attain the bold line.
As a processor for a graphic controller, there has been known a processor described in pages 522-589 of the “Hitachi Microcomputer 8/16-Bit Microcomputer Peripheral LSI” (HD63484) published from the Hitachi, Ltd. in Nov. 1985.
Representative drawing functions of the processor interpret and execute 38 kinds of graphic drawing commands, for example, to draw a line, to draw a circle, to paint a graphic form, to copy a graphic image, and the like. Moreover, the processor has several kinds of drawing and arithmetic operation modes. Particularly, when a conditional replacement is used, color drawing functions can be developed, for example, to specify a particular background color, to designate a drawing inhibit color, and to draw an image with a priority assigned to color data.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a graphic processing system which enables the graphic processor to access the system memory so as to increase the speed of the drawing operation on the system memory and in which, when a parallel processing is executed by a plurality of processors, fundamental information such as a character font to be commonly used is located in the system memory so as to be shared among the processors.
Another object of the present invention is to provide a graphic processing apparatus in which processing of a pixel is accomplished on through a write operation so as to generate and to draw graphic data including a line, an arc, and the like.
Still another object of the present invention is to provide a graphic processing apparatus in which a microprogram to achieve the coordinate calculation and a microprogram to execute the memory address calculation are separated from each other so as to improve the describability or the describing capability of a program.
Further, another object of the present invention is to provide a graphic processing apparatus including a multi-way branch method improving the efficiency of a microprogram.
Another object of the present invention is to provide a graphic processing apparatus having an efficient method of debugging a microprogram in which a microprogram in execution is halted at a desired address, internal inform
Katsura Koyo
Kikuchi Masahiko
Matsuo Shigeru
Sato Jun
Sone Takashi
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