Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
2001-08-21
2002-12-10
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S501000, C345S559000, C345S565000
Reexamination Certificate
active
06492992
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high speed image processing apparatus having microprocessors for inputting and outputting data, collecting data and displaying a graphic pattern in a raster scan type CRT display and having a drawing function controlled by a microprogram stored in a microprogram memory.
2. Description of the Prior Art
Most of prior art CRT controllers control only the display function and have no drawing function. See, for example, U.S. Pat. No. 4,149,264. A graphic processing apparatus which achieves a graphic processing function using an integrated circuit has been known but it merely processes monochromatic graphic pattern data representing each pixel by one bit. However, as the information processing system becomes more and more complex, the image processing for a multi-color or multi-tone image is frequently required and processing, speed for such processing is a problem. For example, when image data is to be updated in the multi-color (n-color) or multi-tone (n-tone) processing system, the same image processing is repeated n times, or when a one-bit one pixel is to be displayed the image processing is repeated n times or when a one-bit pixel is to be displayed the image processing is repeated n times. Accordingly, processing time is n times as long as that for binary image processing. One processing apparatus may be provided for each of n display memories but this increases the scale and the complexity and increases the burden on a central processing unit.
Assume a drawing process in which a line in an X-Y coordinate space having an origin is drawn between two points P
S
(X
S
, Y
S
) and P
E
(X
E
, Y
E
). A gradient of the line is calculated based on the coordinates of the two points and coordinates of points on the line are calculated. Thus, the graphic pattern data for each point is prepared and stored. The above process is sequentially carried out for all points on the line. Since the calculated coordinates are different information than the memory addresses of the display memory in which the graphic pattern data are to be written, the calculated coordinates (logical addresses) must be translated to the display memory addresses (physical addresses). Since each word of the display memory includes one or more pixels of data, the calculated logical address is translated into two physical addresses, first to the display memory address, and second to a bit address representing a pixel position.
In order to translate the logical address to the physical address, the physical address of the origin point and the horizontal size of the display memory must be known. Since the logical address (X, Y) represents a relative position to the origin point, the physical address can be calculated by adding to or subtracting from the physical address of the origin point a product of the horizontal size of the display memory multiplied by Y, in the vertical (Y) direction, and a quotient of the logical address X divided by the number of pixels in one word, in the horizontal (X) direction. A residue produced when the logical address X is divided by the number of pixels in one word is used as a bit address. In this manner, the physical address for processing the graphic pattern data is obtained.
However, in the past, the calculation of the logical address and the translation to the physical address were done by a software program. Accordingly, when a general purpose microprocessor is used, many microseconds are required to store one pixel of data in the display memory, and high speed processing is not achieved.
In graphic pattern processing apparatus which generates graphic display data, the graphic display data is transferred in the display memory. Processing speed therein is also a problem.
Assume that pixel data is to be transferred to another pixel position. Usually, each word of the memory stores data of a plurality of horizontally contiguous pixels. Accordingly, when pixel data is to be transferred to another pixel position, a shifting operation to align the bit positions or selecting an operation of source pixel data is required to align the bit positions for operation. In the past, the transferring was done by a software program. For example, when data in a rectangular area is to be transferred, additional steps for moving pointers for designating source pixels and destination pixels, and counting the number of times of transfer are required. As a result, when a general purpose microprocessor is used, many microseconds are required to transfer one pixel of data and hence a high processing speed is not attained.
The present invention provides an image processing method and apparatus which enables high speed processing of memory updating of multi-color, and multi-tone data, pattern drawing and pixel data transfer.
Related prior art of this type of image processing apparatus is disclosed in Great Britain Patent GB 2,087,696A.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a graphic and image processing apparatus which can draw a pattern of a multi-color or multi-tone data having each pixel represented by a plurality of bits, at substantially the processing speed as that for binary image data.
It is another object of the present invention to provide an image processing apparatus which can calculate an address in a display memory at a high speed based on a logical address of an image.
In accordance with one aspect of the present invention, the image processing apparatus comprises means for sequentially calculating pixel addresses each including information for designating a display memory address and a pixel position in one-word display data at that address, based on display control data, means for logically operating on drawing data for the designated pixel bits for the calculated one-word pixel address based on pixel position information, and means for writing the logically operated on data into the display memory address.
In accordance with another aspect of the present invention, the image processing apparatus comprises logical address operation means for providing a logical address representing a relative position of a pattern to an origin point based on display control data, and means for calculating a physical address in a display memory based on the logical address.
In accordance with another aspect of the present invention, the image processing apparatus comprises means for calculating a shift amount based on information for designating a pixel position in a source word and information for designating a pixel position in a destination word, when display data is to be transferred in a graphic pattern display memory, and shift means for multiple shifting of a plurality of bits.
In accordance with a further aspect of the present invention, the image processing apparatus comprises a command register for storing a command code contained in a command supplied as a display control data, a decoder for decoding a portion of the command code stored in the command register to generate a type and a sign of operation to be carried out for a current coordinate, a code register for storing the output of the decoder, means for calculating pixel coordinates on a graphic pattern display memory based on a control signal and means for designating a position on the graphic pattern display memory based on the coordinates.
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Kajiwara Hisashi
Katsura Koyo
Maejima Hideo
Antonelli, Terry, Soutt & Kraus, LLP
Hitachi , Ltd.
Tung Kee M.
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