Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1999-09-01
2004-01-20
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S571000, C711S102000, C711S104000, C711S105000
Reexamination Certificate
active
06680736
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device applied to a graphics display system.
2. Description of the Related Art
A graphics display system shows and transmits information to a user through digital images. The images are characters, numbers, graphs, and pictures. In many applications, the digital images are transmitted to users by a display device such as a raster scan video monitor and a printer. The images are stored as digital data in a storing apparatus, i.e., a mapping memory and are shown on a display by a certain manipulation.
Therefore, a mapping memory for storing the data of the display is necessary in the graphics display system. Mapping process is necessary for expressing the data stored in a digital type as an image on the display. The data of a predetermined memory cell of the mapping memory is processed as the image in a predetermined byte on the display by the mapping.
A drade-off is generated between the performance/speed of a microprocessor for generating data shown on the video display and the read/write time of the memory. Therefore, such elements must be considered in the application of the graphics display system. Other elements considered are the width and height of the display, the size of RAM, and the center direction of a system, i.e., line oriented or tile oriented.
Suppliers of devices used in such an application manufacture devices having various selection types. Accordingly, designers and users can use the various types of devices for various purposes.
The line oriented graphics display system generates and stores data according to a sequential order so that a line is displayed on the display one by one. Namely, the writing of data into the mapping memory and the reading of data from the mapping memory to the display are performed by one bit and by one line. The display of the tile oriented graphics display system is divided grids having the same sizes and shapes, called tiles. The size and shape of the tiles are one among the elements selected by system designers and users. For example, the tiles can be square or rectangle. Since the tile oriented graphics display system simultaneously refreshes a screen, it has an advantage in respect to an operation speed. Namely, the refresh efficiency is improved by processing a plurality of data bits as a pack. The mapping memory which can simultaneously input and output many items of data are required for performing the tile oriented display and mapping. The tile oriented graphic display system is not so widely applied due to the restriction of the number of pads which can be loaded in a conventional semiconductor memory device.
However, a merged memory with logic in which a semiconductor memory device and a logic circuit are realized in a chip was recently developed. Accordingly, the restriction of the number of the pads of the semiconductor memory device is somewhat relaxed.
A conventional semiconductor memory device is constructed to be suitable for the line oriented graphics display system. Namely, the conventional semiconductor memory device is designed so that a row is accessed and maintained when a plurality of columns are selected. Such an operation mode is called a page mode. The operation of the page mode improves the entire operation speed of the semiconductor memory device. When all the columns arranged along an array are accessed when a row is accessed, 50 through 70 percent of access time is reduced.
In the tile oriented graphics display system, the data stored in the mapping memory is shown on the display in units of a pixel formed of a byte of a plurality of rows and a plurality of columns. Therefore, the semiconductor memory device having a high degree of freedom which can simultaneously process data of a plurality of lines and a plurality of columns is used as the mapping memory for the tile oriented graphics display system.
However, such a conventional semiconductor memory device has a structure in which a column address is changed and data is accessed in a row. Therefore, the conventional semiconductor memory device is suitable for the line oriented graphics display system. However, the conventional semiconductor memory device lowers a speed efficiency in the tile oriented graphics display system.
SUMMARY OF THE INVENTION
To solve the above problem(s), it is an object of the present invention to provide a semiconductor memory device having a high degree of freedom in the selection of columns, thus being suitable for a tile oriented graphics display system.
It is another object of the present invention to provide a mapping apparatus using the semiconductor memory device.
To achieve the first objective, there is provided a semiconductor memory device having a multi-bit operation mode for simultaneously inputting and outputting
2
m
(m is a natural number) items of data, comprising a first memory array including a plurality of memory cell groups for inputting/outputting m items of first data in the multi-bit operation mode and a second memory array including a plurality of memory cell groups for inputting/outputting m items of second data in the multi-bit operation mode, wherein the rows of the plurality of memory cell groups of the first memory array and the rows of the plurality of memory cell groups of the second memory array are selected by the same row address and the columns of the plurality of memory cell groups of the first memory array and the columns of the plurality of memory cell groups of the second memory array are independently selected.
To achieve the second objective, there is provided a graphics display system, comprising a display showing an image of a title structure comprised of a plurality of pixels, a mapping memory for mapping an image by supplying data to the display and storing the image shown in the display as data and a mapping controlling portion for calculating mapping addresses and mapping coefficients identical to the data of the pixel on the display and providing the mapping addresses and the mapping coefficients to the display, wherein the mapping memory comprises a first memory array including a plurality of memory cell groups for inputting/outputting m items of first data in a multi-bit operation mode and a second memory array including a plurality of memory cell groups for inputting/outputting m items of second data in the multi-bit operation mode, wherein the rows of the plurality of memory cell groups of the first memory array and the rows of the plurality of memory cell groups of the second memory array are selected in the same row address and the columns of the plurality of memory cell groups of the first memory array and the columns of the plurality of memory cell groups of the second memory array are independently selected.
According to the semiconductor memory device of the present invention, the degree of freedom of the columns becomes higher. In the graphics display system using the semiconductor memory device as the mapping memory, the number of changes of the row address is minimized, thus all the tiles perform image processing. Accordingly, it is possible to minimize time for refreshing the tile oriented display.
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Bella Matthew C.
Monestime Mackly
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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