Graphic accelerator reducing and processing graphics data

Computer graphics processing and selective visual display system – Computer graphics processing – Attributes

Reexamination Certificate

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Details

C345S600000

Reexamination Certificate

active

06693644

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a graphic accelerator that carries out image display processing. More particularly, the present invention relates to a graphic accelerator that improves processing speed by reducing graphics data, and a drawing method thereof.
2. Description of the Background Art
Modernly, a graphic accelerator which is a dedicated LSI (Large Scale Integrated Circuit) to execute the drawing process of an image at high speed is employed in personal computers, video game machines and the like in order to output a fine image of visual realism.
FIG. 1
is a block diagram of a typical computer or video game's graphics apparatus including a conventional graphic accelerator. This graphics apparatus includes a CPU (Central Processing Unit)
101
controlling the entire apparatus, a main memory
102
, a graphic accelerator
103
, a control circuit
104
controlling generation of a timing signal and data input/output with respect to main memory
102
and graphic accelerator
103
, an image memory
105
used in processing graphics data, and a CRT (Cathode Ray Tube)
106
where an image is displayed.
Graphic accelerator
103
includes a drawing instruction execution unit
107
processing the input drawing instruction and converting parameters into graphics data with pixels forming the screen as the basic unit, an image memory control unit
108
writing drawing image with pixels as the basic unit from drawing instruction execution unit
107
into image memory
105
and reading out graphics data from image memory
105
, a screen data output unit
109
converting graphics data read out from image memory
105
into data of the display format of CRT
106
, and a DAC (Digital/Analog Converter)
110
converting digital signals output from screen data output unit
109
into analog signals. The processing contents carried out by drawing instruction execution unit
107
and screen data output unit
109
are well known in the field of art. Therefore, detailed description thereof will not be provided.
In the graphics apparatus of
FIG. 1
, the data transfer speed of an image memory interface bus
111
between image memory control unit
108
in graphic accelerator
103
and image memory
105
often becomes the bottleneck in determining the drawing processing performance. This is because the data transfer speed between graphic accelerator
103
and image memory
105
is significantly low with respect to the processing speed of graphic accelerator
103
since graphic accelerator
103
and image memory
105
are formed of separate semiconductor components.
As a method of improving the data transfer speed between graphic accelerator
103
and image memory
105
, the method of increasing the bus width of image memory interface bus
111
, and the method of improving the data transfer frequency of image memory
105
are known. However, the method of increasing the bus width of image memory interface bus
111
induces the problem of increasing the area of the circuit substrate where graphic accelerator
103
is mounted, increasing the circuit complexity due to bus width expansion, increasing the area for mounting image memory
105
, and the like. The method of improving the data transfer frequency of image memory
105
is disadvantageous in that an image memory of a large capacity and of short access time is not available at a low cost. Thus, there was a problem that it is difficult to provide a graphic accelerator improved in processing speed without increasing the cost.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a graphic accelerator that can improve the processing speed of graphics processing.
Another object of the present invention is to provide a graphic accelerator that can reduce the capacity of the image memory used in processing graphics data.
A further object of the present invention is to provide a graphic accelerator that can reduce the circuit scale of the arithmetic unit and the like.
Still another object of the present invention is to provide a drawing method that can improve the speed of drawing processing.
A still further object of the present invention is to provide a drawing method that can reduce the capacity of the image memory used in processing graphics data.
Yet a further object of the present invention is to provide a drawing method that can reduce the circuit size of the arithmetic unit and the like.
According to an aspect of the present invention, a graphic accelerator includes a first conversion unit converting pixel information represented by the colorimetric system using stimulus values of the three primary colors such as the RGB format into pixel information of a format including a luminance component and a color difference component, a data compression unit compressing the color difference component of the pixel information converted by the first conversion unit, a drawing unit generating graphics data according to the luminance component converted by the first conversion unit and the color difference component compressed by the data compression unit, a data expansion unit expanding the graphics data generated by the drawing unit, and a second conversion unit converting the graphics data expanded by the data expansion unit into graphics data represented by the aforementioned colorimetric system.
Since the drawing unit generates graphics data according to the luminance component converted by the first conversion unit and the color difference component compressed by the data compression unit, the amount of data transfer of the graphics data can be reduced to improve the processing speed. Also, the capacity of the image memory storing graphics data can be reduced since the amount of graphics data is reduced.
According to another aspect of the present invention, a drawing method includes the steps of converting pixel information represented by the colorimetric system using stimulus values of the three primary colors such as the RGB format into pixel information of a format including a luminance component and a color difference component, compressing the color difference component of the converted pixel information, generating graphics data according to the converted luminance component and the compressed color difference component, expanding the generated graphics data, and converting the expanded graphics data into graphics data represented by the aforementioned colorimetric system.
Since graphics data is generated according to the converted luminance component and the compressed color difference component, the data transfer amount of graphics data can be reduced to improve the processing speed. Since the amount of graphics data is reduced, the capacity of the image memory storing graphics data can be reduced.


REFERENCES:
patent: 5262847 (1993-11-01), Rodriguez et al.
patent: 5920322 (1999-07-01), Ulichney
patent: 1314095 (1993-03-01), None
patent: 64-53680 (1989-03-01), None
patent: 2-100465 (1990-04-01), None
patent: 4-307894 (1992-10-01), None
patent: 8-294142 (1996-11-01), None
patent: 8-336163 (1996-12-01), None

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