Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-08-02
2011-08-02
Graybill, David E (Department: 2894)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
07989338
ABSTRACT:
Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
REFERENCES:
patent: 6022808 (2000-02-01), Nogami et al.
patent: 6023100 (2000-02-01), Tao et al.
patent: 6117770 (2000-09-01), Pramanick et al.
patent: 6228759 (2001-05-01), Wang et al.
patent: 6268291 (2001-07-01), Andricacos et al.
patent: 6426289 (2002-07-01), Farrar
patent: 6440849 (2002-08-01), Merchant et al.
patent: 6500749 (2002-12-01), Liu et al.
patent: 6589874 (2003-07-01), Andricacos et al.
patent: 6633085 (2003-10-01), Besser et al.
patent: 6713875 (2004-03-01), Farrar
patent: 6717236 (2004-04-01), Lopatin et al.
patent: 7115498 (2006-10-01), Adem
patent: 7169700 (2007-01-01), Chang et al.
patent: 7183629 (2007-02-01), Engelmann et al.
patent: 2002/0115292 (2002-08-01), Andricacos et al.
patent: 2003/0015793 (2003-01-01), Merchant et al.
patent: 2003/0160330 (2003-08-01), McTeer
patent: 2004/0005773 (2004-01-01), Lopatin et al.
patent: 2005/0046031 (2005-03-01), Engelmann et al.
patent: 2006/0027460 (2006-02-01), Chang et al.
patent: 2006/0286797 (2006-12-01), Zhang et al.
Ensinger, W.; Modification of mechanical and chemical surface properties of metals by plasma immersion ion implantation; Surface and Coatings Technology; 1998; pp. 341-352; continued . . . 100-101; Elsevier Sciences B.V.; 12 pages.
Ogawa et al.; Stress-Induced Voiding Under Vias Connected to Wide Cu Metal Leads; Pub. date unknown—received by rep May 16, 2004; 10 pages.
Kumar et al.; Semiconductor applications of plasma immersion ion implantation technology; Bull. Mater. Sci.; Nov. 2002; pp. 549 to 551; vol. 25, No. 6; 3 pages.
Bu Xiaomei
Chok Kho Liep
Hsia Liang Choo
Lee Tae Jong
See Alex
Globalfoundries Singapore Pte. Ltd.
Graybill David E
Horizon IP Pte Ltd
LandOfFree
Grain boundary blocking for stress migration and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Grain boundary blocking for stress migration and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Grain boundary blocking for stress migration and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2720298