Gradual on output buffer circuit including a reverse turn-off ap

Details Gradual on output buffer circuit including a reverse turn-off ap Gradual on output buffer circuit including a reverse turn-off ap

1993-10-06

1995-06-13

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 29, 326 90, 326 91, 326 86, H03K 1716, H03K 190175

Patent

active

054246539

ABSTRACT:
An output buffer circuit is provided which significantly reduces ground/Vcc bounce and glitches of signals provided to an integrated circuit. The circuit includes a plurality of transistors for providing a drive potential at the output of the device. The transistors are coupled such that they increase in size from the input to the output of the output buffer circuit. A control circuit provides control signals for sequentially turning off the transistors from the largest to smallest device thereby substantially reducing the Vcc bounce and glitches of the signals provided to the integrated circuit by the output buffer circuit.

REFERENCES:
patent: 4495626 (1985-01-01), Brunin et al.
patent: 4719369 (1988-12-01), Asano et al.
patent: 4725747 (1988-02-01), Stein et al.
patent: 4885485 (1989-12-01), Leake et al.
patent: 5036222 (1990-07-01), Davis
patent: 5036232 (1991-07-01), Jungert et al.
patent: 5061864 (1991-10-01), Rogers
patent: 5097149 (1992-03-01), Lee
patent: 5099148 (1992-03-01), McClure et al.
patent: 5103118 (1992-04-01), Peterson

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