Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-02
2006-05-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07039896
ABSTRACT:
The present invention is directed to a method and apparatus for making mask edge corrections using a gradient method for high density chip designs. The present invention uses a newly defined cost function.
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patent: 6269472 (2001-07-01), Garza et al.
patent: 6611953 (2003-08-01), Filseth et al.
patent: 6813757 (2004-11-01), Aton et al.
patent: 6928634 (2005-08-01), Granik et al.
patent: 2004/0015808 (2004-01-01), Pang et al.
patent: 2005/0015233 (2005-01-01), Gordon
Aleshin Stanislav V.
Egorov Eugeni E.
Medvedeva Marina M.
Rodin Sergei B.
LSI Logic Corporation
Smith Matthew
Suiter West Swantz pc llc
Tat Binh
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