Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-11-02
2003-07-01
Nelms, Divid (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S683000
Reexamination Certificate
active
06586320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to forming conductive structures within an integrated circuit device, and in particular to forming silicides on conductive structures within an integrated circuit device. Still more particularly, the present invention relates to forming silicides of variable metal concentration as a portion of an integrated circuit device.
2. Background of the Invention
Polysilicon layers are frequently utilized for transistor gates, interconnects, and other conductive structures within integrated circuits. To reduce the resistance of the conductive structure, doped polysilicon is often employed in those applications. While this reduces the resistance of the conductive structure, the sheet resistance remains higher than desired, e.g., between 20 and 40 Ohms/square (&OHgr;/□). When used as a long distance conductor, the doped polysilicon interconnect may introduce a significant transmission delay.
One method to improve the sheet resistance of doped polysilicon in gate applications that does not require additional masking steps is to combine the polysilicon with a refractory metal. Refractory metal silicide films such as tungsten silicide and titanium silicide are formed on the polysilicon conductive structures (with the resulting silicide often being referred to as a “polycide”) in integrated circuits, particularly transistor gates. This process results in an improved sheet resistance, on the order of 1 to 5 Ohms/square. The use of a silicide gate reduces interconnect resistance and allows the gate to be used as a moderate long-distance interconnect. Silicide is also increasingly employed in semiconductor fabrication to reduce the contact resistance to both the gate and the source/drain conductors.
Silicide formation between a silicon and a refractory metal can be accomplished by several means. Silicides may be formed by depositing a refractory metal layer on an existing polysilicon layer, then annealing the two layers at a sufficiently high temperature to form a silicide at the interface. Alternatively, silicides may be deposited through sputter deposition from a refractory metal silicide target or by chemical vapor deposition utilizing gaseous reactants including both the refractory metal and silicon.
In conventional silicide processes, a silicide with a uniform metal concentration or stochimetric ratio (that is, the ratio x/y in Si
x
R
y
for a silicide formed with refractory metal R) is utilized. However, due to post silicide thermal cycles, such as poly oxidation, annealing steps, and the like, severe problems are known to occur. For example, when the Si/W ratio is low in tungsten silicide, delamination of the silicide from the underlying structure and tungsten oxidation may occur. To overcome these problems, silicon-rich silicides are commonly employed, but result in high resistivities, require large film thickness, provide poor step coverage, and degrade production throughput in both etch and deposition steps. Currently, Si/W ratios of between 2.7 and 3.3—with a resistivity of about 60 &mgr;&OHgr;-cm—are employed in tungsten silicides as a compromise between sheet resistivity versus delamination and oxidation. As a result, transistor performance, and overall circuit performance, may be limited.
It would be desirable, therefore, to form silicides in integrated circuit devices with low sheet resistance and reduced likelihood of either delamination or metal oxidation.
SUMMARY OF THE INVENTION
A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.
REFERENCES:
patent: 4954852 (1990-09-01), Lemnios
patent: 5635765 (1997-06-01), Larson
patent: 5654219 (1997-08-01), Huber
patent: 5863393 (1999-01-01), Hu
patent: 5907784 (1999-05-01), Larson
patent: 6153452 (2000-11-01), Merchant et al.
patent: 6214711 (2001-04-01), Hu
patent: 19840236 (1999-07-01), None
patent: 0 785 574 (1997-07-01), None
patent: 10303144 (1998-11-01), None
Fang Ming
Wang Fuchao
Jorgenson Lisa K.
Le Dung A
Munck William A.
Nelms Divid
STMicroelectronics Inc.
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