Graded MOS transistor junction formed by aligning a sequence of

Details Graded MOS transistor junction formed by aligning a sequence of Graded MOS transistor junction formed by aligning a sequence of

1998-04-24

2000-07-04

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438719, 438738, 438753, H01L 2100

Patent

active

060838469

ABSTRACT:
A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a lateral surface to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. Preferably, the multi-layer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The oxide is grown upon the polysilicon to align a source/drain implant. Either before the source/drain implant or after the source/drain implant, the oxide and polysilicon partially consumed by the oxide is removed to provide a lateral surface to which an MDD implant aligns. A combination of etch stop, polysilicon spacer and grown possibly sacrificial oxide allows a greater ease by which multiple implants can be forwarded into junctions of either an NMOS or PMOS transistor.

REFERENCES:
patent: 4172260 (1979-10-01), Okabe et al.
patent: 4463491 (1984-08-01), Goldman et al.
patent: 4652897 (1987-03-01), Okuyama et al.
patent: 4672419 (1987-06-01), McDavid
patent: 4737828 (1988-04-01), Brown
patent: 4788663 (1988-11-01), Tanaka et al.
patent: 4818714 (1989-04-01), Haskell
patent: 4818715 (1989-04-01), Chao
patent: 4843023 (1989-06-01), Chiu et al.
patent: 4868617 (1989-09-01), Chiao et al.
patent: 4949136 (1990-08-01), Jain
patent: 4951100 (1990-08-01), Parrillo
patent: 4952825 (1990-08-01), Toshida
patent: 4969639 (1990-11-01), Bergonzoni
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5015598 (1991-05-01), Verhaar
patent: 5091763 (1992-02-01), Sanchez
patent: 5153145 (1992-10-01), Lee et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5216268 (1993-06-01), Chen et al.
patent: 5234850 (1993-08-01), Liao
patent: 5241203 (1993-08-01), Hsu et al.
patent: 5258319 (1993-11-01), Inuishi et al.
patent: 5274261 (1993-12-01), Chen
patent: 5298446 (1994-03-01), Onishi et al.
patent: 5324974 (1994-06-01), Liao
patent: 5332914 (1994-07-01), Hazani
patent: 5334870 (1994-08-01), Katada et al.
patent: 5371394 (1994-12-01), Ma et al.
patent: 5386133 (1995-01-01), Hiroki et al.
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5422506 (1995-06-01), Zamapian
patent: 5444282 (1995-08-01), Yamaguchi et al.
patent: 5473184 (1995-12-01), Murai
patent: 5477070 (1995-12-01), Nam
patent: 5494838 (1996-02-01), Chang et al.
patent: 5498555 (1996-03-01), Lin
patent: 5608240 (1997-03-01), Kumagai
patent: 5663586 (1997-09-01), Lin
patent: 5665620 (1997-09-01), Nguyen et al.
patent: 5679589 (1997-10-01), Lee et al.
patent: 5714413 (1998-02-01), Brigham et al.
patent: 5719425 (1998-02-01), Akram et al.
patent: 5766969 (1998-06-01), Fulford, Jr. et al.
patent: 5783475 (1998-07-01), Ramaswami
patent: 5793089 (1998-08-01), Fulford, Jr. et al.
patent: 5827769 (1998-10-01), Aminzedeh et al.
patent: 5830794 (1998-11-01), Kusunoki et al.
patent: 5837572 (1998-11-01), Gardner et al.
patent: 5847428 (1998-12-01), Fulford, Jr. et al.
patent: 5869866 (1999-02-01), Fulford, Jr. et al.
patent: 5869879 (1999-02-01), Fulford, Jr. et al.
Wolf et al., Silicon Processing for the VLSI Era, Vol. 1: Process Technology, Lattice Press 1986, p. 183.

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