Method for manufacturing local interconnect

Details Method for manufacturing local interconnect Method for manufacturing local interconnect

1997-12-29

2000-07-04

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

438753, 438754, 438755, H01L 2128

Patent

active

060838477

ABSTRACT:
A method for manufacturing local interconnects includes providing a substrate with a gate oxide layer thereover, a first gate electrode and a second gate electrode above the gate oxide layer, spacers on the sidewalls of the gate electrodes, including a first spacer on one sidewall of the first gate electrode and a second spacer on the other sidewall of the first gate electrode. Then, a photoresist layer is applied while keeping the first spacer exposed. Subsequently, the first spacer is removed to expose the sidewall of the first gate electrode. Then, a metal silicide layer is formed over the first gate electrode, the second gate electrode, the one sidewall of the first gate electrode and the substrate. Wet etching is used to remove the first spacer so that local interconnects are automatically formed after the self-aligned silicide processing operation.

REFERENCES:
patent: 5086017 (1992-02-01), Lu
patent: 5229307 (1993-07-01), Vora et al.
patent: 5312781 (1994-05-01), Gregor et al.
patent: 5856226 (1999-01-01), Wu

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