Graded MOS transistor junction formed by aligning a sequence of

Details Graded MOS transistor junction formed by aligning a sequence of Graded MOS transistor junction formed by aligning a sequence of

1997-01-10

1998-08-11

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257900, H01L 2976

Patent

active

057930899

ABSTRACT:
A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a lateral surface to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. Preferably, the multi-layer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The oxide is grown upon the polysilicon to align a source/drain implant. Either before the source/drain implant or after the source/drain implant, the oxide and polysilicon partially consumed by the oxide is removed to provide a lateral surface to which an MDD implant aligns. A combination of etch stop, polysilicon spacer and grown possibly sacrificial oxide allows a greater ease by which multiple implants can be forwarded into junctions of either an NMOS or PMOS transistor.

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