Graded LDD implant process for sub-half-micron MOS devices

Details Graded LDD implant process for sub-half-micron MOS devices Graded LDD implant process for sub-half-micron MOS devices

1995-10-05

1998-02-17

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257917, 438231, 438307, H01L 2976

Patent

active

057194246

ABSTRACT:
A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N-LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

REFERENCES:
patent: 4939386 (1990-07-01), Shibata et al.
patent: 5021851 (1991-06-01), Haken et al.
patent: 5217910 (1993-06-01), Shimizu et al.
Reliability and Performance of Submicron LDD NMOSFET's With Buried-As-n-Impurity PRofiles, IEDM Tech. dig., 1985, pp. 246-249. C.Y. Wei, et al.
Buried and Graded/Buried LDD Structures for Improved Hot-Electron Reliability, IEEE Electron Device Lett., vol. EDL-7, np. 6, Jun. 1986.

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