Graded LDD implant process for sub-half-micron MOS devices

Details Graded LDD implant process for sub-half-micron MOS devices Graded LDD implant process for sub-half-micron MOS devices

1997-10-14

2000-04-04

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257408, 257900, H01L 29784

Patent

active

060464720

ABSTRACT:
A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

REFERENCES:
patent: 4939386 (1990-07-01), Shibata et al.
patent: 5021851 (1991-06-01), Haken et al.
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5716862 (1998-02-01), Ahmad et al.
patent: 5770505 (1998-06-01), Om et al.
#C.Y. Wei, et al., "Reliability and Performance of Submicron LDD NMOSFET's with buried-As-n-Impurity Profiles", IEDM Tech, Dig., pp. 246-249 (1985).
#"Buried and Grded/Buried LDD Structures for Improved Hot-Electron Reliability", IEEE Electron Device Lett., vol. EDL-7 pp. 6 (Jun. 1986).

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