Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2011-04-05
2011-04-05
Knoll, Clifford H (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C711S141000
Reexamination Certificate
active
07921251
ABSTRACT:
In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.
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Co-Pending U.S. Appl. No. 10/832,607 filed Apr. 27, 2004, entitled “Transmitting Peer-to-Peer Transactions Through a Coherent Interface” by Kenneth C. Creta, et al.
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Blankenship Robert G.
Hum Herbert H. J.
Spink Aaron T.
Intel Corporation
Knoll Clifford H
Trop Pruner & Hu P.C.
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