Global reset and zero detection for a memory system

Details Global reset and zero detection for a memory system Global reset and zero detection for a memory system

1989-10-10

1991-11-19

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including signal comparison

365201, G11C 1140

Patent

active

050671103

ABSTRACT:
A tag bit is provided for each row of a memory array. The tag bit is zero is all of the bits in a row are zeros. A detector scans input data to test for all zeros and the tag bit is reset to zero. The output signals for a row are forced to zero when the tag bit for that row is zero.

REFERENCES:
patent: 4321695 (1982-03-01), Redwine et al.

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