Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-04-06
2004-03-02
Auve, Glenn A. (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C327S018000
Reexamination Certificate
active
06701398
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuit architectures having an on-chip high speed bus with multiple medium speed devices, on or off the chip, attached to the bus, and in particular relates to command or data transfer between devices over the bus and to handshaking methods and circuitry for acknowledging receipt by a target device of a command or data packet placed on the bus.
BACKGROUND ART
In typical bus systems, the bus is at the same speed or slower than the devices attached to it. The system bus is located on a printed wiring board, with processor and memory chip modules being bonded to the board, and the bus is subject to capacitance and inductance delays that slow information transfer over the bus between the various chips. In such systems, it is the bus rather than the devices on the bus which are the primary bottleneck in information transfers, and calculations of latency and bandwidth are concerned with arbitration delays for obtaining access to the bus.
When entire systems, or significant portions thereof, are integrated on a chip, the bus itself may also be integrated onto the chip. Such on-chip buses are very fast, typically about six to ten times faster than those located on printed wiring boards. An on-chip bus operating at a clock rate of 640 to 800 MHz can transfer data at a rate of about 4 to 5 GBytes/sec. At that speed the bus is so fast it is effectively transparent. The bus is significantly faster than even the fastest target device attached to the bus. For example, a DRAM has a peak sustainable volume transfer rate of 0.8 GBytes/sec. Even with two DRAM modules, their total bandwidth is only 1.6 GBytes/sec, still significantly less than the bus bandwidth. This means that the speed of the system is not limited by the speed of the bus, but by the speed of the target devices on the bus.
In order to avoid having one device tie up the bus while it waits to receive data requested from another device on the bus, a split transaction bus may be used. In this way, the bus can have many transactions in progress at the same time. Each data read operation occurs in two steps: read initiation followed by read completion. There is a delay between read initiation and read completion. This delay is the time required for the target to decode the request, get the requested data and send it back to the requesting device (master). During this time, neither the master device nor the target device is on the bus. Rather, after the master device has sent its data read command in a first bus cycle, it then releases the bus. Thus, while the master device is waiting for the completion of its read, the bus can support other transactions. Meanwhile, the target device processes the received request, and only when the read data is ready does it arbitrate for the bus and send the requested data to the master device. The transfer of the data to the requesting device completes the read cycle.
One problem that can occur with split transaction buses is that of a non-existent target device. If there is no device to receive a command, then data does not come back. However, since split transaction buses normally have a delay between a read command and eventual receipt of data, a nonresponse can go unnoticed. The requesting device continues to wait indefinitely. What is needed is a handshaking method that provides a transaction acknowledge by the target device. It is desired that the master device get a indication within two clock cycles of sending a request that the designated target device has received that request. This requirement of essentially immediate feedback is tough to do on a split transaction bus without tying up the bus for the time required to return an acknowledgement, or alternatively requiring the target to arbitrate for the bus for an acknowledgement cycle separate from the data return cycle or cycles.
In U.S. Pat. No. 5,666,559, Wisor et al. describes a system in which peripheral devices receiving data provide an acknowledge signal to the central unit. A time-out counter is provided, and if the time-out period expires prior to return of an acknowledge signal, the control unit asserts an error flag and initiates an interrupt routine.
It is an object of the present invention to provide a synchronous transaction acknowledge circuit with nonresponse detection for a fast split-transaction bus.
SUMMARY OF THE INVENTION
The object is met by providing the bus with a separate transaction acknowledge line, by providing each target device with a driver circuit that flips the current state of the transaction acknowledge line to its opposite state whenever the target device receives a command intended for it, and by providing the bus system with an acknowledge-detection circuit that looks for whether the transaction acknowledge line's state has flipped. This scheme provides immediate feedback to the requesting master device that its command has been received by the designated target device. If the state of the transaction acknowledge line remains unchanged, a nonexistent target device is indicated.
A bus idle default device (BIDD) may be provided to drive the transaction acknowledge line when no other device is driving the bus. In one embodiment, the BIDD may include a circuit that detects a nonresponse from a nonexistent target device and which then generates a dummy response for the requesting master device. The dummy data is flagged to indicate that it is not the requested data. Alternatively, detection of the absence of a transaction acknowledge may be carried out by a detector in the bus interfaces of every master device.
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Auve Glenn A.
Cradle Technologies, Inc.
Schneck Thomas
Vu Trisha
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