Global access bus architecture

Electrical computers and digital data processing systems: input/ – Intrasystem connection

Reexamination Certificate

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Details

C711S154000, C712S205000

Reexamination Certificate

active

06981077

ABSTRACT:
Global access bus architecture includes a master request bus and a slave request bus separated from each other and pipelined. The global access bus architecture includes packet input global access bus software code for flow of data packet information from a flexible input data buffer to an analysis machine, packet data global access bus software code for flow of packet data between a flexible data input bus and a packet manipulator, statistics data global access bus software code for connection of an analysis machine to a packet manipulator, private data global access bus software code for connection of an analysis machine to an internal memory engine, lookup global access bus software code for connection of an analysis machine to an internal memory engine, results global access bus software code for providing flexible access to an external memory, and results global access bus software code for providing flexible access to an external memory.

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“Tagged Inter Processor Communication Bus for Multiprocessor Systems” IBM Technical Disclosure Bulletin, Aug. 1991, vol. 34, issue 3, pp. 115-121.

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