Glitchless clock switch

Details Glitchless clock switch Glitchless clock switch

1998-12-23

2001-07-24

Heckler, Thomas M. (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

C713S400000

Reexamination Certificate

active

06266780

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the switching between multiple clock signals. More particularly, it relates to the smooth, glitchless switching between two or more clock signals for use by sensitive circuitry such as a microprocessor, microcontroller, or digital signal processor.
2. Background of Related Art
Power management of a digital processing system is important, especially in today's world where miniaturization is realized with smaller batteries, smaller heat sinks, etc.
It is well known that in general, faster operation of a particular digital circuit requires more power than if the same digital circuit were to be operated at a slower speed. Thus, one technique for managing the power of a particular processing system is to vary the system clock speed depending upon the current needs of the system. A faster system clock may be used during times that a maximum amount of processing capability takes precedence over power consumption. Inversely, a slower system clock may be used during periods of low activity in an effort to conserve power resources.
It is common in power management techniques to provide a plurality of accurate clock sources generated, e.g., from separate crystals. The separate clock sources are typically separate and asynchronous from one another.
To place a particular processing system in a low power mode, a slower system clock signal is typically switched in. Similarly, to enter a higher power mode, the slower clock signal is switched out and a faster clock signal is switched in as a new system clock signal.
In order to swap the system clock from high speed to low speed, or from low speed to high speed, assurance must be provided that a clock ‘spike’ or ‘glitch’ does not occur in the system clock. A glitch corresponds to a frequency of the system clock which is faster than the desired or required clock frequency. A glitch in the system clock raises the possibility that the digital processing system utilizing the system clock may malfunction.
Clock switching control signals are typically synchronized with a current system clock (i.e., a clock source currently in use as the system clock signal), particularly if generated by the digital processing system itself. Thus, because the available clock sources are typically mutually asynchronous with one another, clock switching control signals are typically asynchronous with the “future” system clock (i.e., generated by the clock source being switched to).
Thus, a synchronizer is typically used in the generation of clock switching control signals. Synchronizers generally provide that the clock switching control signals first turn off the current system clock, and then turn on the future system clock.
Accordingly, because a conventional synchronizer is used to synchronize clock switching control signals directly, the synchronization process becomes complex and unreliable. This is especially true in the case of a transition between a very fast system clock signal and a very slow system clock signal.
The design of a glitchless clock switch using a synchronizer requires a significant amount of effort to ensure a proper timing relationship for the clock switching control signals, e.g., mutual-locking logic. Some clock sources (e.g. a fast PLL clock source) may require the use of auxiliary clock signals (such as the internal clock signal from the PLL) to assist in ensuring a smooth transition in the clock switching process. Thus, clock switching circuit design is typically customized for the particular application, leading to increased expense in each new design, and lower reliability from design to design due to the increased complexity of the clock switching circuitry and because each clock switching circuit is newly designed.
Accordingly, there is a need for a glitchless clock switching technique which is reliable, simple, and/or reusable from design to design.
SUMMARY OF THE INVENTION
In accordance with one aspect of the principles of the present invention, a finite state machine for a glitchless clock switch comprises an on state, a stop state, and an idle state.
A glitchless clock switch in accordance with another aspect of the present invention comprises a plurality of clock signals each being adapted to have three states of operation. Logic is adapted to detect when all of the plurality of clock signals are simultaneously in one of the three states of operation, and to activate a corresponding all-idle signal. The all-idle signal is synchronized to a newly selected clock signal when switching from one of the plurality of clock signals to another of the plurality of clock signals.
A method of switching between a plurality of clock signals in accordance with yet another aspect of the present invention comprises transitioning all of the plurality of clock signals into a respective IDLE state. The respective IDLE states of all of the plurality of clock signals are synchronized to a selected one of the plurality of clock signals. The selected one of the plurality of clock signals is output once the respective IDLE states of all of the plurality of clock signals are synchronized by the step of synchronizing.


REFERENCES:
patent: 5561288 (1996-10-01), Stevens
patent: 5577075 (1996-11-01), Cotton et al.
patent: 5604754 (1997-02-01), Itskin et al.
patent: 5652536 (1997-07-01), Nookala et al.
patent: 5848281 (1998-12-01), Smalley et al.
patent: 6163583 (2000-12-01), Lin et al.

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