Glitchless clock selection circuit

Details Glitchless clock selection circuit Glitchless clock selection circuit

2006-02-21

2006-02-21

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S600000, C326S093000, C327S298000

Reexamination Certificate

active

07003683

ABSTRACT:
A clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK1and CLK2, where no assumptions are made regarding frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START1and START2(both active high), are used to start and stop the clocks. As long as one clock is active, the START signal of the other clock will not have any effect. The invention includes interlock circuitry that ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signal.

REFERENCES:
patent: 5726593 (1998-03-01), Ruuskanen
patent: 6275546 (2001-08-01), Miller et al.
patent: 6453425 (2002-09-01), Hede et al.
patent: 6535048 (2003-03-01), Klindworth
patent: 6563349 (2003-05-01), Mavila et al.
patent: 6600345 (2003-07-01), Boutaud

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