Glitch-free receivers for bi-directional, simultaneous data bus

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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C326S059000, C326S022000

Reexamination Certificate

active

06842044

ABSTRACT:
A structure and method for eliminating glitches at the output of a receiver receiving signals sent to one end of a bi-directional, simultaneous transmission line. The receiver comprises two comparators, a logic circuit, a glitch detector, and a programmable delay unit. The two comparators convert a three-state digital signal on the transmission line into two two-state digital signals so that the logic circuit can understand. When a glitch occurs at the output of the logic circuit, also the output of the receiver, caused by the transitions on the output of one of the comparators and a first signal being sent to the other end of the transmission line reaching the logic circuit not at the same time, the glitch detector causes the programmable delay unit to adjust delay to the propagation path of the first signal to the logic circuit so as to eliminate the cause of the glitch.

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Mooney et al., A 900 Mb/s Bidirectional Signaling Scheme; IEEE Journal of Solid-State Circuits, vol. 30, No. 12, Dec. 1995, pp. 1538-1543.

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