Glitch-free memory address decoding circuits and methods and...

Details Glitch-free memory address decoding circuits and methods and... Glitch-free memory address decoding circuits and methods and...

2006-04-18

2006-04-18

Vital, Pierre M. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C345S567000

Reexamination Certificate

active

07032083

ABSTRACT:
Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.

REFERENCES:
patent: 6215712 (2001-04-01), Yanagisawa

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