Glitch-free clock suspend and resume circuit

Details Glitch-free clock suspend and resume circuit Glitch-free clock suspend and resume circuit

2008-06-30

2011-11-15

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

Inhibiting timing generator or component

C327S099000, C327S407000, C327S098000, C365S027000, C375S373000, C326S021000

Reexamination Certificate

active

08060771

ABSTRACT:
Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a high or a low state, instantaneously with the suspend signal. There is no restriction on either the suspend pulse width or position in relation to the input clock. The asynchronous logic implementation is using standard cell logic gates. The circuit functionality is not dependent on the manufacturing technology, i.e. CMOS, bipolar, BI-CMOS, GaAs, etc. implementations are all valid.

REFERENCES:
patent: 5448597 (1995-09-01), Hashimoto
patent: 5574753 (1996-11-01), Vartti et al.
patent: 5623223 (1997-04-01), Pasqualini
patent: 5668982 (1997-09-01), Davis
patent: 5808486 (1998-09-01), Smiley
patent: 6021501 (2000-02-01), Shay
patent: 6154046 (2000-11-01), Kermani
patent: 6239626 (2001-05-01), Chesavage
patent: 6266780 (2001-07-01), Grundvig et al.
patent: 6269043 (2001-07-01), Batcher
patent: 6292044 (2001-09-01), Mo et al.
patent: 6324652 (2001-11-01), Henderson et al.
patent: 6429689 (2002-08-01), Allen et al.
patent: 6472909 (2002-10-01), Young
patent: 6529033 (2003-03-01), Park et al.
patent: 6580776 (2003-06-01), Chang et al.
patent: 6600345 (2003-07-01), Boutaud
patent: 6639449 (2003-10-01), De La Cruz et al.
patent: 6819150 (2004-11-01), Santosa et al.
patent: 7039146 (2006-05-01), Chiu
patent: 7295044 (2007-11-01), Bucossi et al.
patent: 7332978 (2008-02-01), Tiwari et al.
patent: 7679408 (2010-03-01), Hailu et al.
patent: 7724059 (2010-05-01), Kapur
patent: 2001/0043105 (2001-11-01), Zhang et al.
patent: 2003/0048118 (2003-03-01), Nguyen et al.
patent: 2003/0226054 (2003-12-01), Benno et al.
patent: 2004/0104751 (2004-06-01), Campbell
patent: 2005/0017779 (2005-01-01), Osvaldella
patent: 2005/0168263 (2005-08-01), Fukuda et al.
patent: 2006/0006909 (2006-01-01), Morigaki
patent: 2007/0152719 (2007-07-01), Wu et al.
patent: 08392006.6-1233 (2008-11-01), None

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