Glitch-eliminator circuit

Details Glitch-eliminator circuit Glitch-eliminator circuit

1992-08-20

1995-02-07

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 21, 326 93, 327292, 327551, H03K 1716

Patent

active

053878256

ABSTRACT:
One embodiment of the present invention is a digital circuit (10) for providing glitch-free data in an asynchronous environment, the circuit comprising: an input circuit (11) for accepting data; combinational logic circuitry (12) for accepting the data from the input circuit (11 ) and manipulating the data to provide output data, wherein a delay in data flow occurs while the combinational logic manipulates the data; and an output circuit (14) for accepting the output data at a predetermined period after the receipt of data by the input circuit. Preferably, the predetermined period is at least as long as the delay in data flow.

REFERENCES:
patent: 4748417 (1988-05-01), Spengler
patent: 4929850 (1990-05-01), Breuninger
patent: 4972518 (1990-11-01), Matsuo
patent: 5029279 (1991-07-01), Sasaki et al.

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