Germanium-containing dielectric barrier for low-k process

Details Germanium-containing dielectric barrier for low-k process Germanium-containing dielectric barrier for low-k process

2007-04-02

2010-10-19

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S751000, C257S762000, C257S767000, C257SE23141, C257SE23161, C257SE23154

Reexamination Certificate

active

07816789

ABSTRACT:
A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.

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Awaya, N., et al., “Self-Aligned Passivation Technology for Copper Interconnection Using Copper-Aluminum Alloy,” Jpn. J. Appl. Phys., Mar. 1997, vol. 36, pp. 1548-1553, Part 1, No. 3B.
Gosset, L. G., et al., “Self Aligned Barrier Approach: Overview on Process, Module Integration and Interconnect Performance Improvement Challenges,” IITC, 2006, pp. 84-86, IEEE.
Ko, T., et al., “High Performance/Reliability Cu Interconnect with Selective CoWP Cap,” 2003 Symposium on VLSI Technology Digest of Technical Papers, 2 pages.
Usami, T., at al., “Highly Reliable Interface of Self-aligned CuSiN process with Low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond,” IITC, 2006, pp. 125-127, IEEE.

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