Generic methodology to support chip level integration of IP...

Details Generic methodology to support chip level integration of IP... Generic methodology to support chip level integration of IP...

2007-03-26

2010-02-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07669155

ABSTRACT:
A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.

REFERENCES:
patent: 5644498 (1997-07-01), Joly et al.
patent: 6877139 (2005-04-01), Daga
patent: 7475000 (2009-01-01), Cook et al.
patent: 2005/0240892 (2005-10-01), Broberg et al.

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