Generic architecture and system for a programmable serial...

Details Generic architecture and system for a programmable serial... Generic architecture and system for a programmable serial...

2006-09-26

2006-09-26

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C710S100000, C341S050000

Reexamination Certificate

active

07114093

ABSTRACT:
A high-speed programmable serial port having a finite state machine, a clock generator capable of controlling shifting of bits from a shift register and a shift register having a bit counter capable of maintaining a numbered count of data bits in a serial output. The clock generator and shift register reduce the burdens on a finite state machine, thus improving data throughput and the ability to provided data according to a multitude of data protocols.

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AD6522, “Digital Baseband Processor Specification”, Version 1.7b, Dec. 22, 2000 ADI Publication, pp. 98-120.

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