Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-24
2004-05-04
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06732346
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the automated layout of semiconductor devices within an integrated circuit. More specifically, the present invention relates to the generation of route rules in the layout of semiconductor devices.
2. Description of the Related Art
The design of complex and high performance integrated circuits requires balancing the often conflicting requirements of robust circuits, high performing circuits, and reasonable design time and cost. The semiconductor design process is very complex and typically involves the use of numerous software tools that aid in the generation, simulation or analysis of the design. Even with the use of such tools, the design process of a complex integrated circuit may require hundreds of man-years of labor and considerable computation.
The design process may be thought of being divided into four main parts. The first part is logic design where the desired logic function is created. The next step is circuit design where the logic design is described at the transistor level, with the size of each transistor specified. The next step is designing the topographical configuration of the transistors and the associated interconnecting wires, which is known as the layout step. Lastly, the analysis (verification) step is where the expected electrical and physical properties of this topology are extracted from the design, and simulations are performed to verify that the circuit will operate at the desired speed, under the expected operating conditions, and will have acceptable reliability. Typically, problems are found in the analysis step that must be corrected in one or more of the preceding steps.
Broadly speaking, the methods used to perform logic design may be placed into one of two classes: synthesis and or custom design. Synthesized logic is described by the designer in some type of high level programming language, and then synthesized by a software tool into the logic gates needed to implement the desired logic function. Custom logic design, on the other hand, involves the designer designing or specifying the logic gates, perhaps down to the transistor level.
Circuit design methods differ and may be automated, partially automated, or manual. Generally, however, circuit design is the process of modifying logic gates (while retaining the same logical function) and specifying transistor sizes in those gates so that performance goals such as speed, power, area, and reliability are met. Since the design has not yet been described at a detailed geometrical or topographical level, the process of circuit design must involve estimates or predictions of the actual layout.
After layout, such things as wire lengths, widths, spacings, etc. can be extracted from the design. The design can be simulated with these “actual” parasitics and evaluated relative to the performance goals.
It is well known in the art that dynamic style CMOS circuit families can provide the highest performance in digital integrated circuits. Gates in these logic families are generally characterized by the use of a clocked precharge device to initialize a dynamic node in the logic gate and one or more transistors that conditionally discharge the dynamic node. To achieve the highest performance, the discharge or evaluation operation is made as fast as possible or practical so that logic operations can proceed at maximum frequency.
One type of dynamic logic, N-NARY logic or NDL, is better described in U.S. Pat. No. 6,069,497, which is incorporated by reference for all purposes into this disclosure. NDL uses 1 of N signals for conveying information between different NDL logic circuits. One of N signals are described in copending patent application, U.S. patent application Ser. No. 09/019,278, and also in U.S. Pat. No. 6,202,194, both of which are incorporated by reference for all purposes into this disclosure. And finally, NDL uses a logic synchronization technique that is better described in U.S. Pat. No. 6,118,304, which is also incorporated by reference for all purposes into this specification. All of the above patents and applications comprise FAST14 Technology and all are owned by Intrinsity, Inc., the assignee of this disclosure.
One of the hazards inherent in dynamic logic families is associated with a conditional discharge action. In order to make the discharge of the dynamic node as fast as possible, the precharge transistors are turned off during the evaluate phase. Keeper transistors are often present to prevent the dynamic node from losing charge due to parasitic leakage. However, such keeper transistors are made fairly weak so as to not impede the discharge action. The hazard that occurs is that the dynamic node is discharged inadvertently causing the gate to evaluate into an incorrect logic state.
There are several ways that charge can be lost from the dynamic node in dynamic logic family gates. The charge loss from these different mechanisms can be cumulative so that, even though one mechanism by itself may not be sufficient to discharge the gate, multiple charge loss mechanisms may act together to incorrectly discharge a gate. Furthermore, even if one isolated dynamic gate does not experience sufficient charge loss on its dynamic node to cause incorrect operation of that gate, a series of dynamic gates, each experiencing some partial charge loss, may interact in such a way that incorrect logical operation results.
One of the most important mechanisms of charge loss in dynamic gates is the presence of noise on the inputs to the logic gate. For example, if the dynamic node of a gate is precharged to a high voltage and conditionally discharged to a low voltage, the discharged transistors of the gate are typically n-channel transistors. If the inputs to the gate are all intended to remain low in a certain cycle, then the dynamic node is intended to remain high. If one or more inputs to the gate have noise so that their voltage level rises above the intended low voltage for a short time, the n-channel transistors may turn on enough to cause an incorrect discharge or partial discharge of the dynamic node.
Input signals to dynamic gates may experience noise from several unrelated sources. The main source of noise is from direct capacitive or inductive coupling by other signals. Another source of input noise is the partial discharge of a dynamic gate that generates the signal in question because the partial discharge results in the output voltage of the gate changing slightly (or greatly) from its intended value. Yet another source of noise is voltage supply differential among different dynamic gates. For example, a differential in the ground supply voltage between two gates can result in the output of the first gate, intended to be low, being perceived by the second gate as being at a voltage greater than the intended low voltage.
Another important mechanism for charge loss in dynamic gates is charge sharing within the evaluate or discharge circuit. For example, if the evaluate circuit is comprised of a network of n-channel transistors (often called the n-tree), then different nodes within the network of n-tree transistors may be at different voltages due to prior conditions in the gate. If a node that is at a relatively low voltage is coupled to the dynamic node, then the lower voltage node may partially discharge the dynamic node even if there is not a conducting path all the way to ground.
From the above discussion, we know that noise may be added to a circuit from within a gate, from the relationship between gates, or from the wiring that connects the gates together. Sufficient noise may be injected into the circuit at one point to cause failure. More difficult to analyze is the case where smaller amounts of noise are injected at several points in the circuit. Taken individually, each contribution of noise is not sufficient to cause failure. Taken together, however, the cumulative effect can result in failure.
Some or all of the previously discussed conditions may occur in a given gate under certain operating
Glowka Donald W.
Horne Stephen C.
Vijayan Gopal
Booth Matthew J.
Intrinsity, Inc.
Whitmore Stacy A.
Wright Karen S.
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