Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2004-01-28
2008-10-28
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S735000, C714S738000
Reexamination Certificate
active
07444559
ABSTRACT:
A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.
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Cheryl E. Praeger, Linear Feedback Shift Registers, Chapter 4, pp. 1-10, available at http://www.maths.uwa.edu.au/˜praeger/teaching/3CC/WWW/chapter4.html on Aug. 18, 2003.
Greeff Roy E.
Swanson Travis E.
Chung Phung M
Jones Day
Micro)n Technology, Inc.
Pencoske Edward L.
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