Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Patent
1995-06-07
1998-04-07
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
711211, 711212, 395307, 395886, 395653, G06F 1200, G06F 1300
Patent
active
057377642
ABSTRACT:
A method and circuitry for generating column addresses for a memory based upon signals on an address bus in a computer system, are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes circuitry for receiving address lines from the address bus, and for receiving control register bits indicating a particular memory array type. The memory array type indicates the number of the address bits which are to be forwarded to the memory as the column address, rather than as the row address. The memory is of a dynamic random access memory (DRAM) type, for which row and column addresses are time-multiplexed over the same lines. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for controlling the access to configuration registers, and circuitry for determining the sizes of individual memory banks in the memory.
REFERENCES:
patent: 4739473 (1988-04-01), Ng et al.
patent: 5040153 (1991-08-01), Fung et al.
patent: 5237672 (1993-08-01), Ing-Simmons
patent: 5274768 (1993-12-01), Traw et al.
patent: 5287531 (1994-02-01), Rogers, Jr. et al.
patent: 5301292 (1994-04-01), Hilton et al.
patent: 5307320 (1994-04-01), Farrer et al.
patent: 5317709 (1994-05-01), Sugimoto
patent: 5408129 (1995-04-01), Farmwald et al.
patent: 5513331 (1996-04-01), Pawlowski et al.
patent: 5572692 (1996-11-01), Murdoch et al.
Linley Gwennap, Microprocessor Report, "TI Shows Integrated X86 CPU for Notebooks", vol. 8, No.2. Feb, 14, 1994, pp.5-7.
ACC Micro, ACC 2056 3.3V Pentium Single Chip Solution for Notebook Applications, Rev. 1.1, pp. 1-1--1-10.
ACC Micro, ACC 2066 486/386DX Notebook Enhanced-SL Single Chip AT, Rev. 1.2, Oct. 11, 1993 pp.1-1--1.10.
PicoPower, Redwood Technical Reference Manual,Databook 3.0P, Jul. 8, 1994, pp.i-iv, 18,19, 87-89.
ACC Micro, ACC Microelectronics Product Guide.
VIA Technologies, Inc., Energy Star-Compliant System Logic Solutions, Brochure.
OPTi, 82C895 Single Chip True Green PC Chipset.
OPTi, Blackhawk 486 Desktop Chipset.
EFAR, EC802G One Chip32 Bits PC/AT Core Logic, Technical Reference Manual, 1994, 11-14, 25,29.
ETEQ Micro, Buffalo ET 9000, 486 Write Back Cache "AT" Single Chip, Rev 03, May 1994, pp. 1-8.
ETEQ Micro, Panda 82C390SX, Single Chip 386 SX Direct Mapped Cache solution, Rev 0.1, Oct. 1991, pp. 1-4, Rev.0.2, Apr. 1992, pp. 5-10.
EFAR, Swift-Ide, 386 Chip UP Grade 486, POWERset Pentium PCI/ISA Chip Set, 1994.
OPTi Python Chipset for Pentium Processors, 82C546 & 82C547 Data Book, Version 1.0, May 1994, pp. 1-3, 37,38,41,43,45-52,65,66,69,70,72.
Symphony Laboratories, Wagner 486 PC/AT Chip Set, Rev A.2,Features, Block Diagram, pp. 1-1--1-8.
UMC Super Energy Star Green File, Version 4.0, Preliminary UM8881F/8886F, Apr. 15, 1994, pp. 1, 7-18.
UMC Super Energy Star Green File, Version 4.0, Preliminary UM8498F/8496F/82C495F, Apr. 15, 1994, pp.1-3, 17-19.
UMC Super Energy Star Green File, Version 4.0, Preliminary UM846F, Apr. 15, 1994, pp.6-8, 17-19.
OPTi, Viper Notebook Chipset, Preliminary Data Book, Ver.0.2, 82C556/82C557/82C558N, Jun. 1994, pp. 1-5, 46--67.
Texas Instruments, TACT84500 EISA Chip Set, Designer's Handbook, 1991, pp. 3-1--3-4, 3-42 -3-44.
OPTi 82C802G, System/Power Management Controller, Mar. 1994, pp. 1-14, 19--22, 37.
OPTi 82C596/82C597, Cobra Chipset for Pentium Processors Data Book, Rev. 1.0, Oct. 1994, pp. 1-3, 35-51.
Texas Instruments, TACT84411 Single-Chip 80486 Systems Logic, 1993, pp. 1-1--1-5, 2-1, 2-2, 4-1t13 4-15, 5-28.
Burton Dana L.
Donaldson Richard L.
Gossage Glenn
Kesterson James C.
Texas Instruments Incorporated
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