Generation of memory addresses for accessing a memory...

Details Generation of memory addresses for accessing a memory... Generation of memory addresses for accessing a memory...

2000-06-19

2002-10-08

Ellis, Kevin L. (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

Reexamination Certificate

active

06463518

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to electronic circuit arrangements and integrated circuits incorporating the same, and in particular to address generation logic used to generate addresses for accessing a memory space.
BACKGROUND OF THE INVENTION
As semiconductor fabrication technology advances, designers of integrated circuits are able to integrate more and more functions into a single integrated circuit device, or chip. As such, electronic designs that once required several integrated circuits electrically coupled to one another on a circuit board or module may now be integrated into a single integrated circuit, thereby increasing performance and reducing cost.
One function that has been migrated from discrete circuits to integrated circuits is digital signal processing, which is generally the application of mathematical operations to digitally represented signals. Digital signal processing is utilized in a number of applications, such as to implement filters for audio and/or video signals, to decode information from communications signals such as in wireless or other cellular networks, etc.
Semiconductor fabrication technology has advanced to the point where the logic circuitry that carries out digital signal processing may be carried out by dedicated digital signal processors that execute software programs, referred to herein as DSP programs, to implement specialized DSP algorithms. Moreover, digital signal processors may be embedded in integrated circuits, or chips, with additional logic circuitry to further provide improvements in performance while lowering costs.
Many digital signal processing tasks are characterized by a need to quickly perform repetitive, but relatively simple, mathematical calculations on a large amount of digital data. Multiply-Accumulate (MAC) operations, for example, perform multiplication of two operands and add the result to a running accumulator, and can often be implemented in hardware logic to be performed in a single clock cycle. Multiple MAC units may even be provided so that multiple MAC operations can occur within any given clock cycle. However, some complex filtering operations may require hundreds or thousands of MAC operations to be performed just to calculate one output value at a single point in time.
Given the repetitive nature of many DSP operations, the speed that input data can be retrieved from memory by a digital signal processor, as well as that output data can be written back into memory after being processed (often referred to as memory bandwidth), often has a significant impact on the overall performance of a DSP system.
One manner of increasing memory bandwidth is to utilize multiple communication paths, or buses, to communicate different types of data with a digital signal processor. As an example, a number of conventional DSP designs separate DSP program data and signal data into separate memory spaces, such that separately-accessible program and data memories are used to store DSP program instructions and signal data. Furthermore, digital signal data may be partitioned into multiple memory spaces (often referred to as “X” and “Y” memory spaces) so that multiple data points can be transferred to or from a given memory at a time. Multiple ports, or access paths, into a memory may also be provided, such that multiple access operations can occur in parallel within a given memory.
As an example, a number of conventional DSP designs incorporate dual MAC units, and as such, require four paths into a data memory space (two each in the “X” and “Y” memory spaces) to maintain maximum efficiency. To access four memory locations per cycle, therefore, four addresses must be generated and output to memory in each access cycle.
While generating four addresses typically does not present a significant problem from a circuitry standpoint, encoding four addresses within a processor instruction such as a DSP instruction presents a comparatively greater concern. DSP instructions, like most processor instructions, typically include an opcode field that specifies the type of instruction, and often the addressing mode to be used by the instruction, as well as one or more operand fields that identify either the data to be processed or where such data is located. Since the number of bits required to encode DSP instructions affects the number of instructions available in an instruction set, the Width of the interconnects, logic units, and registers that are required to process those instructions, and the size of the program memory space, it is highly desirable to minimize the number of bits required to encode addresses in any given DSP instruction.
In a number of conventional DSP designs that incorporate dual MAC units, for example, 32-bit instructions are used. For dual MAC operations, 14 bits of a MAC instruction are allocated to opcodes (7 bits for each MAC unit), leaving a total of 18 bits (9 bits for each MAC unit) to specify the locations of the four operands and where to store the results.
Typically, to minimize the number of required bits to encode addresses, a form of indirect addressing is used, where a bank of separate indirect address registers are preloaded with the desired addresses of operands, and where a MAC instruction specifies the locations of one or more indirect address registers from the bank from which to load the desired addresses. Also, it is often desirable to support address post-modification, where the addresses stored in indirect address registers are automatically modified (e.g., incremented or decremented by a fixed value) after the addresses are output from the registers.
Despite the use of indirect addressing, and in part due to the need to support enhancements such as post-modification, it is often not feasible to support the encoding of four independent addresses within a given DSP instruction. As a consequence, a technique known as address correlation is often used, where only two addresses are independently encoded and generated, with the remaining two addresses being generated by modifying the encoded addresses (e.g., by adding fixed offsets to the encoded addresses).
As an example, one of the aforementioned conventional DSP designs utilizes indirect-address MAC instructions having the following syntax:
MAC (r
i
)+postmod,(r
j
)+postmod,a
m
∥MAC (r
i
~),(r
j
~),a
n
where (r
i
) and (r
j
) are specify indirect addressing via selected indirect address registers r
i
and r
j
, postmod specifies the post-modification to apply to each stored address, a
m
and a
n
specify the accumulators to add the results to, and (r
i
~) and (r
j
~) specify the correlated addresses.
The above MAC instruction is encoded in a 32-bit instruction as shown in table I below:
TABLE I
Conventional Dual MAC Instruction
Encoding (Indirect Addressing)
Bits
Total
Field
(per MAC)
Bits
MAC opcode
7
14
Destination accumulator (4 available)
2
4
r
i
indirect address register (4 available)
2
2
r
j
indirect address register (4 available)
2
2
r
i
post-modification (7 types)
3
3
r
j
post-modification (7 types)
3
3
r
i
modification for X correlated addr (4 types)
2
2
r
j
modification for Y correlated addr (4 types)
2
2
Other types of instructions may also use the aforementioned techniques to generate four addresses in a given cycle. A number of drawbacks, however, exist with respect to the use of such techniques.
First, the use of correlated addressing significantly limits the data organization inside the data memory space, since the data needs to be carefully organized to ensure that the data addressed via the correlated addresses is arranged in appropriate offsets from the data addressed via the encoded addresses. Often, hand optimization of program code is also required to minimize the number of processor cycles lost to inefficient data transfer.
Second, the aforementioned techniques typically only support either all reads or all writes to the independent and correlated addresses. Non-standard combinations such as 3 reads and 1 write, 3 writes and 1 read, etc., are typically not supported. As a consequ

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